Configuring I2S to Generate BCLK from Codec Devices & WCLK from McBSP Port
This application note describes a method for interfacing the multichannel buffered serial port (McBSP) to the I²S™ interface of the TLV320AIC32/33/31, the
TLV320AIC3101/3104/3105/3106/3204/3254 and TLV320DAC32 devices such that the bit clock (BCLK) is generated by the audio data converter device and the word clock (WCLK) is generated by the McBSP.
This type of interface is useful in applications where the host processor (with a McBSP interface) can synchronize the audio (with video, for example) by controlling the WCLK,
whereas the data converter device can generate the BCLK depending on the I²S configuration. The McBSP interface is supported in a variety of processors from TI, such as the TMS320C5000/C6000™ digital signal processors (DSPs), the DaVinci™ digital media processors, and OMAP applications processors.