Fractional/IntegerN PLL Basics
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Phase Locked Loop (PLL) is a fundamental part of radio, wireless and telecommunication technology. The goal of this document is to review the theory, design and analysis of PLL circuits. PLL is a simple negative feedback architecture that allows economic multiplication of crystal frequencies by large variable numbers. By studying the loop components and their reaction to various noise sources, we will show that PLL is uniquely suited for generation of stable, low noise tunable RF signals for radio, timing and wireless applications.
This document details basic loop transfer functions, loop dynamics, noise sources and their effect on signal noise profile, phase noise theory, loop components (VCO, crystal
oscillators, dividers and phase detectors) and principles of integerN and fractionalN technology. The approach will be mainly heuristic, with many design examples.
This document is written for designers, technicians and project managers. Design procedures, equations, performance interpretation, CAD and examples are included to help those who have little experience.
