Selection and Solution Guides

Application Notes

AN-1807 FPD-Link II Display SerDes Overview (Rev. B)


TI’s FPD-Link II family of embedded clock LVDS SerDes provide enhanced features, and improved signal quality over prior generations of FPD-Link SerDes devices for Display applications. FPD-Link Chipsets serialized the wide parallel RGB buses down to 4 or 5 pairs of LVDS signaling depending upon the chipset. 18-bit RGB was serialized to three LVDS data lines and a LVDS clock, while 24-bit RGB was serialized to four LVDS data lines and a LVDS clock. This provided a smaller, higher speed video bus and has become the defacto standard for Notebook Display interfaces.