DFT engineer - Methodology development, implementation, experimentation, deployment into projects.

Part of horizontal team. To contribute to other activities in process, reviews and methodology development.

Work with several team leads. Requires good ability to operate independently and across different activities and teams.

Will be moved to product development teams to work on specific projects as required and in phases.

Good knowledge of hardware design, logic design, and working knowledge of CAD software and automation. Knowledge of DFT tools is desirable.

Will be responsible for managing his work, schedules and interaction with other teams.

Opportunity to work on technology / methodology development, to be deployed in future projects in TII and even in other teams in TI.

As part of a very dynamic engineering team, you will be responsible of developing, specifying and verifying System-On-Chip architectures for mobile phone devices.

This mission consists of: Implementation of high complexity digital basebands in 90 and 65 nm technologies, with low power techniques and usage of the most up to date design flows.

Perform physical design verification and timing closure of complex high speed multi-million gate ASIC standard cell designs.

In addition, the selected individual will perform Clock Tree Synthesis, hold fixing and ECO (Engineering Change Order), using the latest physical design EDA tools.

Skills and competencies required :

Extensive knowledge/experience with Magma. (Avant! tool suite would be an asset.)

Experience with STA (Primetime or PTSI) in the following areas: Timing closure, Signal Integrity, OCV, timing constraints, timing libraries, and Clock Tree Synthesis. Scripting/Programming skills would be desirable in such languages as PERL, TCL, AWK, NAWK, SED.

Understanding of synthesis timing driven layout and post-layout timing closure of deep submicron designs.

Knowledge of layout and routing issues from an ASIC or custom SoC background.

Good communication skills.

As part of a very dynamic engineering team, you will be responsible of developing, specifying and verifying System-On-Chip architectures for mobile phone devices.

This mission consists of: Implementation of high complexity digital basebands in 90 and 65 nm technologies, with low power techniques and usage of most up to date design flows Gate and RTL level timing analysis.

Work with teams designing high-speed ASICs Identifying and developing a validation and verification framework for the DBB SOC architecture.

Skills and competencies required :

Design/Methodology Experience with Static Timing Analysis. Primetime-Primetime-SI Timing closure, Signal Integrity, OCV, timing constraints development , timing libraries, Clock tree synthesis analyze. Knowledge of Perl and Tcl preferred.

Good communication skills.

Perform floor - planning, power routing, clock tree expansion, place and route (P&R), and design closure (timing closure, signal integrity, IR drop, DRC / LVS) for complex and high-gate count SoCs (Silicon-on-Chip) in TI's growing Wireless Solutions Group (WSG).

Have a clear understanding of SoC design methodology, especially understand requirements of deep submicron (DSM) designs. Define all the deliverables for hard IPs (digital and analog) required for building SoC.Work with the frontend team to partition design into smaller modules/subsystems and help in deciding soft versus hard implementation of these block to meet time-to-market (TTM) requirements of the product.

Communicate on daily basis with RTL, design verification, and DFT designers to ensure that the design is solid and bug free at module / chip levels.

Work with other design teams to share best practices.Interact with the Software and Systems teams to understand the end application / domain. He / she should work with other chip / component implementation teams to achieve leadership area, performance and power.

Develop expertise in the area of design and mentor other engineers in the team.Keep with the advancements in the area of physical design tools and technologies, and incorporate these in future chips. Knowledge in any or all of the following areas: RTL, design verification, synthesis, STA, and DFT is added plus. Understand process and design challenges of deep submicron (DSM) designs.

Clearly communicate design status, issues, and concerns with chip create design teams and management. Must be willing to work across organizational boundaries to solve the issues, when called upon to do so.

Identify areas in the design process that will improve the SoC design activity and engineer productivity for himself / herself as well as the team.

Should be able to understand system-level details. Should have excellent problem solving skills to resolve complex issues as they occur.

Previous design experience is required. Experience with some of the following is required: P&R with Magma or PC / Astro, Synopsys Primetime / SI, and solid understanding of ASIC design flow along with signal integrity issues. Previous experience of leading an SoC implementation is highly desirable.

Familiarity with some of the following tools is preferred: Synopsys Design Compiler, and functional verifications tools / techniques.Software skills should include: ability to write / debug PERL, TCL, and shell scripts.Experience with the UNIX operating system is required.

Define the Technology roadmap for the SMS Simulation team and system simulation strategy for TI.

The individual will be responsible for shaping the technology behind the TI simulation products and drive the system simulation strategy for TI.

The individual needs to follow industry and academic trends, understand customer's current and future simulation needs, determine the technology improvements needed to meet the challenges, and propose solutions that will help meet these needs.

The individual will be involved in setting the team's strategic directions.

The individual needs to have a deep knowledge of computer architectures - CPU, Memory systems, DMA, Multi-processor architectures, etc.

The individual needs to have strong experience in developing software, appreciation of embedded software development challenges, proven leadership and mentoring skills.

The candidate's participation in industry-wide forums will be desired.