Clock & timing

Clock buffers - easy clock distribution in any system

Low additive jitter and skew with highly flexible input/output formats

Universal buffer diagram

Universal & programmable buffers

Excellent skew and additive jitter performance, accept multiple input formats, configuration with pin strap or serial interface, level translation, reuse one device for multiple projects and selectable output levels, dividers and delays

Fanout buffer diagram

Fanout buffers

Cost-optimized solutions. Scalable families available for all important signal standards: LVCMOS, LVDS, LVPECL, HCSL (PCIe), CML, (LV)TTL

Zero delay buffers

Integrated PLL with feedback loop for delay compensation, compensate flight time of long traces, and recondition poor clock signals without additional delay

Design tools

This online design tool helps you find the right clock for your system by generating complete clock-tree solutions. The tool generates multiple solutions that optimized for performance.

Videos for clock buffers