Clock and Timing

Clock Buffers - easy clock distribution in any system

Low additive jitter and skew with highly flexible input/output formats

Universal buffer diagram

Universal and programmable buffers

Features include: Excellent skew & additive jitter performance, accept multiple input formats, selectable output levels, dividers and delays, configuration with pin strap or serial interface, level translation, reuse one device for multiple projects

Fanout buffer diagram

Fanout buffers

Cost optimized solution. Scalable families available for all important signal standards: LVCMOS, LVDS, LVPECL, HCSL (PCIe), CML, (LV)TTL

Zero delay buffers

Features include: Integrated PLL with feedback loop for delay compensation, compensate flight time of long traces, recondition poor clock signals without additional delay

<Section CTA Link - not authored>
<Horizontal Rule is not displayed>

Videos for Clock Buffers

WEBENCH® Clock Architect

TI's WEBENCH Clock Architect online design tool makes the designer’s life easier by generating complete clock-tree solutions. Multiple solutions are generated, each optimized for performance, cost or board space.

WEBENCH® Designer