Clock Buffers - easy clock distribution in any system
Low additive jitter and skew with highly flexible input/output formats
Universal and programmable buffers
Features include: Excellent skew & additive jitter performance, accept multiple input formats, selectable output levels, dividers and delays, configuration with pin strap or serial interface, level translation, reuse one device for multiple projects
Cost optimized solution. Scalable families available for all important signal standards: LVCMOS, LVDS, LVPECL, HCSL (PCIe), CML, (LV)TTL
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WEBENCH® Clock Architect
TI's WEBENCH Clock Architect online design tool makes the designer’s life easier by generating complete clock-tree solutions. Multiple solutions are generated, each optimized for performance, cost or board space.