Clock buffers - easy clock distribution in any system
Low additive jitter and skew with highly flexible input/output formats
Universal & programmable buffers
Excellent skew and additive jitter performance, accept multiple input formats, configuration with pin strap or serial interface, level translation, reuse one device for multiple projects and selectable output levels, dividers and delays
Cost-optimized solutions. Scalable families available for all important signal standards: LVCMOS, LVDS, LVPECL, HCSL (PCIe), CML, (LV)TTL
This online design tool helps you find the right clock for your system by generating complete clock-tree solutions. The tool generates multiple solutions that optimized for performance.
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