Clocks & timing

Clock buffers – Design & development

Featured evaluation modules

LMK00338 evaluation module

Evaluation platform for the PCIe Gen 1, Gen 2 and Gen 3 clock buffer family with up to 8 outputs

LMK00105 evaluation module

High-performance single-ended fanout clock buffer family with great flexibility, 5 or 10 outputs and 30 fS of additive jitter

LMK00301 evaluation module

High-performance differential fanout clock buffer with great flexibility, up to 10 outputs and 50 fS of additive jitter

CDCLVP1204 evaluation module

Evaluation platform for the high-performance LVPECL buffer with four outputs and less than 100 fS of additive jitter

Featured reference designs

Gigabit Ethernet link aggregator reference design.

SDI video aggregation reference design.

Extended current and voltage measurement using shunts for protection relays reference design.