Clock jitter cleaners & synchronizers – Design & development
Featured evaluation modules
Evaluation module for our ultra-low noise and low-power JESD204B-compliant dual-loop jitter cleaner
Featured reference designs
Featured tools and software
This online design tool helps you find the right clock for your system by generating complete clock-tree solutions. The tool generates multiple solutions that optimized for performance, cost or board space.
Use our TICSPRO-SW software to program the evaluation modules (EVMs) for our PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.