Overview of TI’s DMOS6 fabrication facility
Wafer size 300 mm
Current capacity 14K wafer starts/month
Final capacity 25K wafer starts/month
Production 130-nm copper
90-nm copper

Space
     Waffle table 118K ft²
     Total manufacturing 190K ft²

Outside
   
Shell constructed 1996
Cleanroom certified 3Q00
First tool installed 3Q00
First full-flow silicon 1Q01
130-nm qualification 3Q02
90-nm qualification 4Q04
65-nm qualification Summer 2006
45-nm development In progress

 

 Inside
Links

- Overview
- Press release announcing TI’s 45-nm technology
- Summary of TI’s keynote paper from the 2006 Symposia on VLSI Technology and Circuits
- Other TI papers presented at the 2006 Symposia on VLSI Technology and Circuits
- Overview of TI’s DMOS6 fabrication facility
- TI sub-100-nm process and manufacturing milestones