In
advance of the prestigious 2006 Symposia on VLSI Technology
and Circuits, Texas Instruments announced details regarding
its next-generation process technology. Unveiled just
six months after TI initiated volume production of its
65-nanometer chips, the company’s new 45-nm process
technology will:
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Increase
performance by 30 percent. |
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Reduce
power consumption by 40 percent. |
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Feature
TI’s first use of 193-nm immersion photolithography
for transistor density improvements that dry lithography
is unable to achieve. |
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Produce
what TI believes to be the smallest 45-nm embedded
SRAM memory cells, occupying only 0.24
square microns. |
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Feature
gate lengths as small as 28 nm. |
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Include
the use of an ultra-low-k dielectric that
achieves a k value of 2.5 and reduces interconnect
capacitance by 10 percent. |
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Enhance
transistor performance and minimize leakage
through a collection of strain techniques, including
TI’s first use of SiGe induced strain. |
TI’s
45-nm semiconductors will be manufactured on 300-mm
wafers in the company’s DMOS6 facility in Dallas.
The low-power ASIC design library will be available
by the end of this year, with samples of the first SoC
product delivered in 2007 and initial production in
mid-2008.
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