Short course: Designing for Paradigm Shifts in Microprocessors and Networking: SoC Integration, P. Rickert

Rump session: Power Management: What Are the Device and Circuit Trade Offs; How Will They Be Managed at 45-nm and 32-nm Nodes? U. Ko

Rump session: Complete Integration of SoC Power Management: Reality or Mirage, K. Kunz with panelists from across the industry

Rump session: What Will Be the Next Embedded Memory Workhorse? P. Rickert with panelists from across the industry

Paper: Sub 0.1[m CMOS with Source/Drain Extension Space Formed Using Nitrogen Implantation Prior to Thick Gate Re-Oxidation, J.C. Hu, A. Chatterjee, M. Mehrotra, J. Vu, W.T. Shiau, M. Rodder

Paper: A Single-Tank, Dual-Band Reconfigurable Oscillator, K. Gharpurey, T.L. Hsien from the University of Texas, with S. Venkatraman from TI

Paper: A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Baseband Modem Chip, F. Jumel, P. Royannez, H. Mair, D. Scott, A.E. Rachidi, R. Lagerquist, M. Chau, S. Guruajarao, S. Thiruvengadam, M. Clinton, V. Menezes, R. Hollingsworth, J. Vaccani, F. Piacebello, N. Culp, J. Rosal, M. Ball, F. Ben-Arnar, J. Bouetel, O. Domerego, J.L. Lachese, C. Fournet-Fayard, J. Ciroux, C. Raibaret, U. Ko

- Overview
- Press release announcing TI’s 45-nm technology
- Summary of TI’s keynote paper from the 2006 Symposia on VLSI Technology and Circuits
- Other TI papers presented at the 2006 Symposia on VLSI Technology and Circuits
- Overview of TI’s DMOS6 fabrication facility
- TI sub-100-nm process and manufacturing milestones