Continued chip scaling to smaller process geometries is imperative to achieve the low power, high performance and higher densities that TI embedded processors and wireless products need to give our customers a competitive advantage.
Joint process technology development model
TI’s advanced digital CMOS development team works side-by-side with foundry partners to develop TI-specified processes that are tuned to address the needs of our customers. This includes close monitoring of the latest innovations in materials, lithography and other process technology developments to understand the implications, opportunities and challenges for future product roadmaps. TI uses techniques such as full immersion lithography, embedded SiGe, and high K/metal gate technology to keep customers on the leading edge. In addition, TI works to optimize core CMOS, embedded memory, analog and I/O attributes to optimize products at each node.
High volume advanced digital CMOS development model
- Jointly defined TI process technology
- TI specific models
- Electrical compatibility and design portability
Our foundry and assembly/test partners supplied more than two-thirds of TI’s digital CMOS capacity at the peak of the 65-nanometer (nm) production. They also supply all of TI’s 45-nm and 40-nm capacity, and are expected to supply TI’s 28nm and 20nm capacity in the future.
TI began sampling its first 40-nm products in late 2010 with the introduction of the new TMS320C66x generation of high-performance, multicore DSPs; TI’s single-core C6A816x Integra™ DSP + ARM® micropocessors; and AM389x Sitara™ ARM microprocesors. In early 2011, TI also unveiled its next generation 28-nm OMAP™ 5 platform, transforming the concept of mobile by delivering significant performance and power management enhancements designed to drive best-in-class applications from computation photography to mobile computing. The ARM Cortex™-A15-based OMAP5 applications processors are expected to sample in the second half of 2011.
In our 28-nm test chips, TI continues to push the envelope in SRAM scaling by demonstrating an ultra-small SRAM bit of .12 microns squared that is half the size of our 45-nm cells. In February 2011, TI with long-time university partner MIT also developed a 0.6 volt DSP in 28-nm process, further demonstrating TI’s ability to deliver ultra low power while meeting next generation processing demands.
VP Tom Thorpe on how TI’s advanced CMOS development and hybrid manufacturing strategy supports TI’s Embedded Processing customers
By leveraging the foundries for both development and manufacturing, TI is able to allocate more resources toward innovation at the design level, and differentiation through increased SoC integration and improved scalability for our embedded processing products. This also includes efforts to continue to reduce power consumption and optimize performance across our products.
An example of this is TI’s SmartReflex™ technologies a collection of hardware and software techniques to bring improved power efficiency to portable devices. Integrated in over one billion devices shipped to date, the impact of SmartReflex is tremendous. In our OMAP3430, for example, SmartReflex delivers a 66 percent reduction in active power consumption and 3X reduction of standby power, which allows our customers to deliver a better user experience through their products by offering much longer battery life when running advanced features.
For more about TI's innovation and ongoing investments in research and development, click here.
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