SBAS844 Data sheet

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage range	AVDD19	–0.3	2.1	V
	AVDD	–0.3	1.4
	DVDD	–0.3	1.4
Voltage applied to input pins	INAP, INAM and INBP, INBM	–0.3	AVDD19 + 0.3	V
	CLKINP, CLKINM	–0.3	AVDD + 0.6
	SYSREFP, SYSREFM, SYNCBP, SYNCBM	–0.3	AVDD + 0.6
	SCLK, SEN, SDIN, RESET, PDN, GPIO1, GPIO2, GPIO3, GPIO4	–0.2	AVDD19 + 0.2
Voltage applied to output pins		–0.3	2.2	V
Temperature	Operating free-air, T_A	–40	85	°C
Temperature	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Supply voltage⁽²⁾	AVDD19	1.8	1.9	2.0	V
	AVDD	1.1	1.15	1.25
	DVDD	1.1	1.15	1.2
Temperature	Operating free-air, T_A	–40		85	°C
Temperature	Operating junction, T_J		105⁽¹⁾	125	°C

(1) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.

(2) Always power up the DVDD supply (1.15 V) before the AVDD19 (1.9 V) supply. The AVDD (1.15 V) supply can come up in any order.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADC32RF42	UNIT
		RMP (VQFN)
		72 PINS
R_θJA	Junction-to-ambient thermal resistance	21.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	4.4	°C/W
R_θJB	Junction-to-board thermal resistance	2.0	°C/W
ψ_JT	Junction-to-top characterization parameter	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter	2.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 1.5 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER CONSUMPTION⁽⁴⁾ (Dual-Channel Operation, Both Channels A and B are Active; DDC Bypass Mode⁽³⁾)
I_AVDD19	1.9-V analog supply current	14-bit, bypass mode, f_S = 1.5 GSPS		1150	1969	mA
I_AVDD	1.15-V analog supply current	14-bit, bypass mode, f_S = 1.5 GSPS		604	1079	mA
I_DVDD	1.15-V digital supply current	14-bit, bypass mode, f_S = 1.5 GSPS		1000	1846	mA
P_D	Power dissipation	14-bit, bypass mode, f_S = 1.5 GSPS		4.03	6.95	W
	Global power-down power dissipation			360		mW
ANALOG INPUTS
	Resolution			14		Bits
	Differential input full-scale			1.35		V_PP
V_IC	Input common-mode voltage			1.2⁽⁵⁾		V
R_IN	Input resistance	Differential resistance at dc		65		Ω
C_IN	Input capacitance	Differential capacitance at dc		2		pF
	V_CM common-mode voltage output			1.2		V
	Analog input bandwidth (–3-dB point)	ADC driven with 50-Ω source		3200		MHz
ISOLATION
	Crosstalk isolation between channel A and channel B⁽¹⁾	f_IN = 100 MHz		100		dBc
		f_IN = 900 MHz		99
		f_IN = 1800 MHz		95
		f_IN = 2700 MHz		86
		f_IN = 3500 MHz		85
CLOCK INPUT⁽²⁾
	Input clock frequency		750	1500		MHz
	Differential (peak-to-peak) input clock amplitude		0.5	1.5	2.5	V_PP
	Input clock duty cycle		45%	50%	55%
	Internal clock biasing			1.0		V
	Internal clock termination (differential)			100		Ω

(1) Crosstalk is measured with a –2-dBFS input signal on aggressor channel and no input on the victim channel.

(2) See Figure 32.

(3) Full-scale signal is applied to the analog inputs of all active channels.

(4) See the Power Consumption in Different Modes section for more details.

(5) When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within V_CM ±25 mV for best performance.

7.6 AC Performance Characteristics

typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 1.5 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

PARAMETER		TEST CONDITIONS	NOM	UNIT
SNR	Signal-to-noise ratio	f_IN = 100 MHz, A_OUT = –2 dBFS	62.8	dBFS
		f_IN = 300 MHz, A_OUT = –2 dBFS	62.6
		f_IN = 950 MHz, A_OUT = –2 dBFS	61.1
		f_IN = 1200 MHz, A_OUT = –2 dBFS	60.4
		f_IN = 1350 MHz, A_OUT = –2 dBFS	60.0
		f_IN = 1850 MHz, A_OUT = –2 dBFS	58.9
		f_IN = 2100 MHz, A_OUT = –2 dBFS	57.9
NSD	Noise spectral density averaged across the Nyquist zone	f_IN = 100 MHz, A_OUT = –2 dBFS	151.6	dBFS/Hz
		f_IN = 300 MHz, A_OUT = –2 dBFS	151.4
		f_IN = 950 MHz, A_OUT = –2 dBFS	149.8
		f_IN = 1200 MHz, A_OUT = –2 dBFS	149.1
		f_IN = 1350 MHz, A_OUT = –2 dBFS	148.8
		f_IN = 1850 MHz, A_OUT = –2 dBFS	147.6
		f_IN = 2100 MHz, A_OUT = –2 dBFS	146.7
	Small-signal SNR	f_IN = 950 MHz, A_OUT = –40 dBFS	63.0	dBFS
NF⁽¹⁾	Input noise figure	f_IN = 950 MHz, A_OUT = –40 dBFS	27.7	dB
SINAD	Signal-to-noise and distortion ratio	f_IN = 100 MHz, A_OUT = –2 dBFS	61.4	dBFS
		f_IN = 300 MHz, A_OUT = –2 dBFS	61.0
		f_IN = 950 MHz, A_OUT = –2 dBFS	60.9
		f_IN = 1200 MHz, A_OUT = –2 dBFS	59.9
		f_IN = 1350 MHz, A_OUT = –2 dBFS	59.2
		f_IN = 1850 MHz, A_OUT = –2 dBFS	58.2
		f_IN = 2100 MHz, A_OUT = –2 dBFS	55.8
ENOB	Effective number of bits	f_IN = 100 MHz, A_OUT = –2 dBFS	9.9	Bits
		f_IN = 300 MHz, A_OUT = –2 dBFS	9.8
		f_IN = 950 MHz, A_OUT = –2 dBFS	9.8
		f_IN = 1200 MHz, A_OUT = –2 dBFS	9.6
		f_IN = 1350 MHz, A_OUT = –2 dBFS	9.5
		f_IN = 1850 MHz, A_OUT = –2 dBFS	9.4
		f_IN = 2100 MHz, A_OUT = –2 dBFS	9.0
SFDR	Spurious-free dynamic range	f_IN = 100 MHz, A_OUT = –2 dBFS	67	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	64
		f_IN = 950 MHz, A_OUT = –2 dBFS	70
		f_IN = 1200 MHz, A_OUT = –2 dBFS	67
		f_IN = 1350 MHz, A_OUT = –2 dBFS	66
		f_IN = 1850 MHz, A_OUT = –2 dBFS	64
		f_IN = 2100 MHz, A_OUT = –2 dBFS	58
HD2	Second-order harmonic distortion	f_IN = 100 MHz, A_OUT = –2 dBFS	68	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	64
		f_IN = 950 MHz, A_OUT = –2 dBFS	72
		f_IN = 1200 MHz, A_OUT = –2 dBFS	70
		f_IN = 1350 MHz, A_OUT = –2 dBFS	67
		f_IN = 1850 MHz, A_OUT = –2 dBFS	64
		f_IN = 2100 MHz, A_OUT = –2 dBFS	58
HD3	Third-order harmonic distortion	f_IN = 100 MHz, A_OUT = –2 dBFS	67	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	71
		f_IN = 950 MHz, A_OUT = –2 dBFS	70
		f_IN = 1200 MHz, A_OUT = –2 dBFS	67
		f_IN = 1350 MHz, A_OUT = –2 dBFS	70
		f_IN = 1850 MHz, A_OUT = –2 dBFS	73
		f_IN = 2100 MHz, A_OUT = –2 dBFS	66
HD4, HD5	Fourth- and fifth-order harmonic distortion	f_IN = 100 MHz, A_OUT = –2 dBFS	89	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	84
		f_IN = 950 MHz, A_OUT = –2 dBFS	85
		f_IN = 1200 MHz, A_OUT = –2 dBFS	83
		f_IN = 1350 MHz, A_OUT = –2 dBFS	85
		f_IN = 1850 MHz, A_OUT = –2 dBFS	83
		f_IN = 2100 MHz, A_OUT = –2 dBFS	82
IL spur	Interleaving spur: f_S / 2 – f_IN,	f_IN = 100 MHz, A_OUT = –2 dBFS	91	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	87
		f_IN = 950 MHz, A_OUT = –2 dBFS	83
		f_IN = 1200 MHz, A_OUT = –2 dBFS	82
		f_IN = 1350 MHz, A_OUT = –2 dBFS	82
		f_IN = 1850 MHz, A_OUT = –2 dBFS	82
		f_IN = 2100 MHz, A_OUT = –2 dBFS	80
HD2 IL	Interleaving spur for HD2: f_S / 2 – HD2	f_IN = 100 MHz, A_OUT = –2 dBFS	86	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	87
		f_IN = 950 MHz, A_OUT = –2 dBFS	83
		f_IN = 1200 MHz, A_OUT = –2 dBFS	80
		f_IN = 1350 MHz, A_OUT = –2 dBFS	79
		f_IN = 1850 MHz, A_OUT = –2 dBFS	79
		f_IN = 2100 MHz, A_OUT = –2 dBFS	80
Worst spur	Spurious-free dynamic range (excluding HD2, HD3, HD4, HD5, and interleaving spurs IL and HD2 IL)	f_IN = 100 MHz, A_OUT = –2 dBFS	80	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	82
		f_IN = 950 MHz, A_OUT = –2 dBFS	80
		f_IN = 1200 MHz, A_OUT = –2 dBFS	82
		f_IN = 1350 MHz, A_OUT = –2 dBFS	79
		f_IN = 1850 MHz, A_OUT = –2 dBFS	80
		f_IN = 2100 MHz, A_OUT = –2 dBFS	81
IMD3	Third-order intermodulation distortion	f_IN1 = 940 MHz, f_IN2 = 960 MHz, A_OUT = –8 dBFS (each tone)	75	dBFS

(1) The ADC internal resistance = 65 Ω, the driving source resistance = 50 Ω.

(2) Minimum values are specified at A_OUT = –3 dBFS.

7.7 Digital Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 1.5 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, GPIO1, GPIO2, GPIO3, GPIO4)
V_IH	High-level input voltage		0.8			V
V_IL	Low-level input voltage				0.4	V
I_IH	High-level input current			50		µA
I_IL	Low-level input current			–50		µA
C_i	Input capacitance			4		pF
DIGITAL OUTPUTS (SDOUT, GPIO1, GPIO2, GPIO3, GPIO4)
V_OH	High-level output voltage		AVDD19–0.1	AVDD19		V
V_OL	Low-level output voltage				0.1	V
DIGITAL INPUTS (SYSREFP and SYSREFM; SYNCBP and SYNCBM; Requires External Biasing)
V_ID	Differential input voltage		350	450	800	mV_PP
V_CM	Input common-mode voltage		1.05	1.2	1.325	V
DIGITAL OUTPUTS (JESD204B Interface: DA[3:0], DB[3:0], Meets JESD204B LV-0IF-11G-SR Standard)
\|V_OD\|	Output differential voltage			700		mV_PP
\|V_OCM\|	Output common-mode voltage			450		mV
	Transmitter short-circuit current	Transmitter pins shorted to any voltage between –0.25 V and 1.45 V	–100		100	mA
z_os	Single-ended output impedance			50		Ω
C_o	Output capacitance	Output capacitance inside the device, from either output to ground		2		pF

7.8 Timing Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

		MIN	NOM	MAX	UNIT
SAMPLE TIMING
	Aperture delay	250		750	ps
	Aperture delay matching between two channels on the same device		±15		ps
	Aperture delay matching between two devices at the same temperature and supply voltage		±150		ps
	Aperture jitter, clock amplitude = 2 V_PP		90		f_S
	Fast overrange latency, ADC sample to FOVR indication on GPIO pins		70		Input clock cycles
t_PD	Propagation delay time: logic gates and output buffer delay (does not change with f_S)		6		ns
SYSREF TIMING⁽¹⁾
t_{SU_SYSREF}	SYSREF setup time: referenced to clock rising edge, 1.5 GSPS	140	70		ps
t_{H_SYSREF}	SYSREF hold time: referenced to clock rising edge, 1.5 GSPS	50	20		ps
	Valid transition window sampling period: t_{SU_SYSREF} – t_{H_SYSREF}, 1.5 GSPS	476			ps
JESD OUTPUT INTERFACE TIMING
UI	Unit interval: 12.5 Gbps	80	100	400	ps
	Serial output data rate	2.5	10.0	12.5	Gbps
	Rise, fall times: 1-pF, single-ended load capacitance to ground		60		ps
	Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps		25		%UI
	Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps		0.99		%UI, rms
	Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps		9.1		%UI, pk-pk

(1) Common-mode voltage for the SYSREF input is kept at 1.2 V.

7.9 Typical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 1.5 GHz, 65536 points FFT, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

SFDR = 73 dBc, SNR = 62.4 dBFS, SINAD = 62 dBFS,
THD = 71 dBc, HD2 = –75 dBFS, HD3 = –78 dBFS,
SFDR (non HD2, HD3) = 85 dBc, IL spur = 81 dBFS

Figure 3. FFT for 100-MHz Input Signal

SFDR = 65 dBc, SNR = 62.3 dBFS, SINAD = 61 dBFS,
THD = 64 dBc, HD2 = –67 dBFS, HD3 = –75 dBFS,
SFDR (non HD2, HD3) = 74 dBc, IL spur = 82 dBFS

Figure 5. FFT for 300-MHz Input Signal

SFDR = 72 dBc, SNR = 60.2 dBFS, SINAD = 60 dBFS, THD = 71 dBc, HD2 = –74 dBFS, HD3 = –87 dBFS, SFDR (non HD2, HD3) = 80 dBFS, IL spur = 80 dBFS

Figure 7. FFT for 1200-MHz Input Signal

SFDR = 59 dBc, SNR = 57.9 dBFS, SINAD = 56 dBFS,
HD2 = –61 dBFS, HD3 = –69 dBFS,
SFDR (non HD2, HD3) = 81 dBc, THD = 58 dBc,
IL spur = 83 dBFS

Figure 9. FFT for 2100-MHz Input Signal

f_IN1 = 940 MHz, f_IN2 = 960 MHz,
A_OUT = –36 dBFS, IMD = 94 dBFS

Figure 11. FFT for Two-Tone Input Signal (–36 dBFS)

Figure 13. Spurious-Free Dynamic Range vs Input Frequency

Figure 15. Signal-to-Noise Ratio vs Input Frequency

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 17. Spurious-Free Dynamic Range vs AVDD Supply and Temperature

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 19. Spurious-Free Dynamic Range vs DVDD Supply and Temperature

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 21. Spurious-Free Dynamic Range vs AVDD19 Supply and Temperature

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 23. Performance vs Clock Amplitude

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 63.8 dBFS,
SFDR (includes IL) = 78 dBc, f_S = 1500 MSPS

Figure 25. FFT in 4x Decimation

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 66 dBFS,
SFDR (includes IL) = 77 dBc, f_S = 1500 MSPS

Figure 27. FFT in 8x Decimation

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 65.9 dBFS,
SFDR (includes IL) = 74 dBc, f_S = 1500 MSPS

Figure 29. FFT in 10x Decimation

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 68.1 dBFS,
SFDR (includes IL) = 80.9 dBc, f_S = 1500 MSPS

Figure 31. FFT in 16x Decimation

SFDR = 65 dBc, SNR = 62.3 dBFS, SINAD = 61 dBFS,
THD = 64 dBc, HD2 = –67 dBFS, HD3 = –73 dBFS,
SFDR (non HD2, HD3) = 89 dBc, IL spur = 81 dBFS

Figure 4. FFT for 185-MHz Input Signal

SFDR = 70 dBc, SNR = 60.8 dBFS, SINAD = 60 dBFS,
THD = 69 dBc, HD2 = –72 dBFS, HD3 = –78 dBFS,
SFDR (non HD2, HD3) = 81 dBc, IL spur = 82 dBFS

Figure 6. FFT for 950-MHz Input Signal

SFDR = 70 dBc, SNR = 58.7 dBFS, SINAD = 58 dBFS,
HD2 = –72 dBFS, HD3 = –75 dBFS,
SFDR (non HD2, HD3) = 79 dBc, THD = 68 dBc,
IL spur = 80 dBFS

Figure 8. FFT for 1850-MHz Input Signal

f_IN1 = 940 MHz, f_IN2 = 960 MHz, A_OUT = –8 dBFS, IMD = 75 dBFS

Figure 10. FFT for Two-Tone Input Signal (–8 dBFS)

Figure 12. Intermodulation Distortion vs Input Amplitude (940 MHz and 960 MHz)

Figure 14. IL Spur vs Input Frequency

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 16. Signal-to-Noise Ratio vs AVDD Supply and Temperature

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 18. Signal-to-Noise Ratio vs DVDD Supply and Temperature

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 20. Signal-to-Noise Ratio vs AVDD19 Supply and Temperature

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 22. Performance vs Amplitude

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 24. Performance vs Clock Duty Cycle

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 65 dBFS,
SFDR (includes IL) = 75 dBc, f_S = 1500 MSPS

Figure 26. FFT in 6x Decimation

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 65.8 dBFS,
SFDR (includes IL) = 74 dBc, f_S = 1500 MSPS

Figure 28. FFT in 9x Decimation

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 66.4 dBFS,
SFDR (includes IL) = 74.1 dBc, f_S = 1500 MSPS

Figure 30. FFT in 12x Decimation

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 AC Performance Characteristics

7.7 Digital Requirements

7.8 Timing Requirements

7.9 Typical Characteristics