SBAS890A March   2019  – July 2019 ADS131M04

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Block Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions: SBAS890
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Clocking and Power Modes
      6. 8.3.6  ΔΣ Modulator
      7. 8.3.7  Digital Decimation Filter
        1. 8.3.7.1 Fast-Startup Response
      8. 8.3.8  DC Block Filter
      9. 8.3.9  Internal Test Signals
      10. 8.3.10 Channel Phase Calibration
      11. 8.3.11 Calibration Registers
      12. 8.3.12 Fast Startup After POR
        1. 8.3.12.1 Startup Following Reset
      13. 8.3.13 Communication Cyclic Redundancy Check (CRC)
      14. 8.3.14 CRC Register Map
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Conversion Modes
        1. 8.4.2.1 Continuous-Conversion Mode
        2. 8.4.2.2 Global-Chop Mode
        3. 8.4.2.3 Power Modes
      3. 8.4.3 Standby Mode
      4. 8.4.4 Current-Detect Mode
    5. 8.5 Programming
      1. 8.5.1 Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  ADC Conversion Data
          1. 8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection
        10. 8.5.1.10 Commands
          1. 8.5.1.10.1 NULL (0000 0000 0000 0000)
          2. 8.5.1.10.2 RESET (0000 0000 0001 0001)
          3. 8.5.1.10.3 STANDBY (0000 0000 0010 0010)
          4. 8.5.1.10.4 WAKEUP (0000 0000 0011 0011)
          5. 8.5.1.10.5 LOCK (0000 0101 0101 0101)
          6. 8.5.1.10.6 UNLOCK (0000 0110 0110 0110)
          7. 8.5.1.10.7 RREG (101a aaaa annn nnnn)
            1. 8.5.1.10.7.1 Reading a Single Register
            2. 8.5.1.10.7.2 Reading Multiple Registers
          8. 8.5.1.10.8 WREG (011a aaaa annn nnnn)
        11. 8.5.1.11 Short SPI Frames
      2. 8.5.2 Synchronization
    6. 8.6 ADS131M04 Registers
      1. 8.6.1  ID Register (Address = 0h) [reset = 1800h]
        1. Table 15. ID Register Field Descriptions
      2. 8.6.2  STATUS Register (Address = 1h) [reset = 500h]
        1. Table 16. STATUS Register Field Descriptions
      3. 8.6.3  MODE Register (Address = 2h) [reset = 510h]
        1. Table 17. MODE Register Field Descriptions
      4. 8.6.4  CLOCK Register (Address = 3h) [reset = F0Eh]
        1. Table 18. CLOCK Register Field Descriptions
      5. 8.6.5  GAIN1 Register (Address = 4h) [reset = 0h]
        1. Table 19. GAIN1 Register Field Descriptions
      6. 8.6.6  RESERVED Register (Address = 5h) [reset = 0h]
        1. Table 20. RESERVED Register Field Descriptions
      7. 8.6.7  CFG Register (Address = 6h) [reset = 600h]
        1. Table 21. CFG Register Field Descriptions
      8. 8.6.8  THRSHLD_MSB Register (Address = 7h) [reset = 0h]
        1. Table 22. THRSHLD_MSB Register Field Descriptions
      9. 8.6.9  THRSHLD_LSB Register (Address = 8h) [reset = 0h]
        1. Table 23. THRSHLD_LSB Register Field Descriptions
      10. 8.6.10 CH0_CFG Register (Address = 9h) [reset = 0h]
        1. Table 24. CH0_CFG Register Field Descriptions
      11. 8.6.11 CH0_OCAL_MSB Register (Address = Ah) [reset = 0h]
        1. Table 25. CH0_OCAL_MSB Register Field Descriptions
      12. 8.6.12 CH0_OCAL_LSB Register (Address = Bh) [reset = 0h]
        1. Table 26. CH0_OCAL_LSB Register Field Descriptions
      13. 8.6.13 CH0_GCAL_MSB Register (Address = Ch) [reset = 8000h]
        1. Table 27. CH0_GCAL_MSB Register Field Descriptions
      14. 8.6.14 CH0_GCAL_LSB Register (Address = Dh) [reset = 0h]
        1. Table 28. CH0_GCAL_LSB Register Field Descriptions
      15. 8.6.15 CH1_CFG Register (Address = Eh) [reset = 0h]
        1. Table 29. CH1_CFG Register Field Descriptions
      16. 8.6.16 CH1_OCAL_MSB Register (Address = Fh) [reset = 0h]
        1. Table 30. CH1_OCAL_MSB Register Field Descriptions
      17. 8.6.17 CH1_OCAL_LSB Register (Address = 10h) [reset = 0h]
        1. Table 31. CH1_OCAL_LSB Register Field Descriptions
      18. 8.6.18 CH1_GCAL_MSB Register (Address = 11h) [reset = 8000h]
        1. Table 32. CH1_GCAL_MSB Register Field Descriptions
      19. 8.6.19 CH1_GCAL_LSB Register (Address = 12h) [reset = 0h]
        1. Table 33. CH1_GCAL_LSB Register Field Descriptions
      20. 8.6.20 CH2_CFG Register (Address = 13h) [reset = 0h]
        1. Table 34. CH2_CFG Register Field Descriptions
      21. 8.6.21 CH2_OCAL_MSB Register (Address = 14h) [reset = 0h]
        1. Table 35. CH2_OCAL_MSB Register Field Descriptions
      22. 8.6.22 CH2_OCAL_LSB Register (Address = 15h) [reset = 0h]
        1. Table 36. CH2_OCAL_LSB Register Field Descriptions
      23. 8.6.23 CH2_GCAL_MSB Register (Address = 16h) [reset = 8000h]
        1. Table 37. CH2_GCAL_MSB Register Field Descriptions
      24. 8.6.24 CH2_GCAL_LSB Register (Address = 17h) [reset = 0h]
        1. Table 38. CH2_GCAL_LSB Register Field Descriptions
      25. 8.6.25 CH3_CFG Register (Address = 18h) [reset = 0h]
        1. Table 39. CH3_CFG Register Field Descriptions
      26. 8.6.26 CH3_OCAL_MSB Register (Address = 19h) [reset = 0h]
        1. Table 40. CH3_OCAL_MSB Register Field Descriptions
      27. 8.6.27 CH3_OCAL_LSB Register (Address = 1Ah) [reset = 0h]
        1. Table 41. CH3_OCAL_LSB Register Field Descriptions
      28. 8.6.28 CH3_GCAL_MSB Register (Address = 1Bh) [reset = 8000h]
        1. Table 42. CH3_GCAL_MSB Register Field Descriptions
      29. 8.6.29 CH3_GCAL_LSB Register (Address = 1Ch) [reset = 0h]
        1. Table 43. CH3_GCAL_LSB Register Field Descriptions
      30. 8.6.30 REGMAP_CRC Register (Address = 3Eh) [reset = 0h]
        1. Table 44. REGMAP_CRC Register Field Descriptions
      31. 8.6.31 RESERVED Register (Address = 3Fh) [reset = 0h]
        1. Table 45. RESERVED Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Power Metrology Applications
      5. 9.1.5 Multiple Device Configuration
      6. 9.1.6 Code Example
      7. 9.1.7 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Voltage Measurement Front-End
        2. 9.2.2.2 Current Measurement Front-End
        3. 9.2.2.3 ADC Setup
        4. 9.2.2.4 Calibration
        5. 9.2.2.5 Formulae
        6. 9.2.2.6 Test Methodology
        7. 9.2.2.7 Results
  10. 10Power Supply Recommendations
    1. 10.1 CAP Pin
    2. 10.2 Power-Supply Sequencing
    3. 10.3 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • 4 simultaneously sampling differential inputs
  • Programmable data rate up to 32 kSPS
  • Programmable gain up to 128
  • Noise performance:
    • 102-dB dynamic range at gain = 1, 4 kSPS
    • 80-dB dynamic range at gain = 64, 4 kSPS
  • Total harmonic distortion: –100 dB
  • High-impedance inputs for direct sensor connection:
    • 300-kΩ input impedance for gains of
      1, 2, and 4
    • 1-MΩ input impedance for gains of
      8, 16, 32, and 64
  • Programmable channel-to-channel phase delay calibration:
    • 244-ns resolution, 8.192-MHz fCLKIN
  • Current detect mode allows for super low power tamper detection
  • Fast startup: first data within 0.5 ms of supply ramp
  • Integrated negative charge pump allows input signals below ground
  • Crosstalk between channels: –120 dB
  • Low-drift internal voltage reference
  • Cyclic redundancy check (CRC) on communications and register map
  • 2.7-V to 3.6-V analog and digital supplies
  • Low power consumption: 3.3 mW at 3-V AVDD and DVDD
  • Package: 20-pin TSSOP or 20-pin WQFN
  • Operating temperature range: –40°C to +125°C