SBAS713C May 2015 – January 2017 ADS54J69
The ADS54J69 is a low-power, wide-bandwidth, 16-bit, 500-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting one or two lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel is directly connected to a wideband digital down-converter (DDC) block. The ADS54J69 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.
The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.
|PART NUMBER||PACKAGE||BODY SIZE (NOM)|
|ADS54J69||VQFNP (72)||10.00 mm × 10.00 mm|
Changes from B Revision (February 2016) to C Revision
Changes from A Revision (January 2016) to B Revision
Changes from * Revision (May 2015) to A Revision