Refer to the PDF data sheet for device specific package drawings
Figure 6-15 shows the recommended oscillator connections when OSC1 of the ZCE package is connected to an LVCMOS square-wave digital clock source and Figure 6-16 shows the recommended oscillator connections when OSC1 of the ZCZ package is connected to an LVCMOS square-wave digital clock source. The LVCMOS clock source is connected to the RTC_XTALIN terminal. The ground for the LVCMOS clock source and VSS_RTC of the ZCZ package should be connected directly to the nearest PCB digital ground (VSS). In this mode of operation, the RTC_XTALOUT terminal should not be used to source any external components. The PCB design should provide a mechanism to disconnect the RTC_XTALOUT terminal from any external components or signal traces that may couple noise into OSC1 through the RTC_XTALOUT terminal.
The RTC_XTALIN terminal has a 10- to 40-kΩ internal pullup resistor which is enabled when OSC1 is disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer.
|ƒ(RTC_XTALIN)||Frequency, LVCMOS reference clock||32.768||kHz|
|Frequency, LVCMOS reference clock stability and tolerance(1)||Maximum RTC error = 10.512 minutes/year||–20||20||ppm|
|Maximum RTC error = 26.28 minutes/year||–50||50||ppm|
|tdc(RTC_XTALIN)||Duty cycle, LVCMOS reference clock period||45%||55%|
|tjpp(RTC_XTALIN)||Jitter peak-to-peak, LVCMOS reference clock period||–1%||1%|
|tR(RTC_XTALIN)||Time, LVCMOS reference clock rise||5||ns|
|tF(RTC_XTALIN)||Time, LVCMOS reference clock fall||5||ns|