SPRS695D September   2011  – January 2016 AM3871 , AM3874

PRODUCTION DATA.  

  1. 1High-Performance System-on-Chip (SoC)
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
    1. 2.1  Device Comparison
    2. 2.2  Device Characteristics
    3. 2.3  Device Compatibility
    4. 2.4  ARM Cortex-A8 Microprocessor Unit (MPU) Subsystem Overview
      1. 2.4.1 ARM Cortex-A8 RISC Processor
      2. 2.4.2 Embedded Trace Module (ETM)
      3. 2.4.3 ARM Cortex-A8 Interrupt Controller (AINTC)
      4. 2.4.4 ARM Cortex-A8 PLL (PLL_ARM)
      5. 2.4.5 ARM MPU Interconnect
    5. 2.5  Media Controller Overview
    6. 2.6  SGX530 Overview
    7. 2.7  Spinlock Module Overview
    8. 2.8  Mailbox Module Overview
    9. 2.9  Memory Map Summary
      1. 2.9.1 L3 Memory Map
      2. 2.9.2 L4 Memory Map
        1. 2.9.2.1 L4 Fast Peripheral Memory Map
        2. 2.9.2.2 L4 Slow Peripheral Memory Map
      3. 2.9.3 DDR DMM TILER Extended Addressing Map
    10. 2.10 Pin Maps
    11. 2.11 Terminal Functions
      1. 2.11.1  Boot Configuration
      2. 2.11.2  Camera Interface (I/F)
      3. 2.11.3  Controller Area Network (DCAN) Modules (DCAN0, DCAN1)
      4. 2.11.4  DDR2/DDR3 Memory Controller
      5. 2.11.5  EDMA
      6. 2.11.6  EMAC [(R)(G)MII Modes] and MDIO
      7. 2.11.7  General-Purpose Input/Outputs (GPIOs)
      8. 2.11.8  GPMC
      9. 2.11.9  HDMI
      10. 2.11.10 I2C
      11. 2.11.11 McASP
      12. 2.11.12 McBSP
      13. 2.11.13 PCI-Express (PCIe)
      14. 2.11.14 Reset, Interrupts, and JTAG Interface
      15. 2.11.15 Serial ATA (SATA) Signals
      16. 2.11.16 SD Signals (MMC/SD/SDIO)
      17. 2.11.17 SPI
      18. 2.11.18 Oscillator/PLL, Audio Reference Clocks, and Clock Generator
      19. 2.11.19 Timer
      20. 2.11.20 UART
      21. 2.11.21 USB
      22. 2.11.22 Video Input (Digital)
      23. 2.11.23 Video Output (Digital)
      24. 2.11.24 Video Output (Analog, TV)
      25. 2.11.25 Reserved Pins
      26. 2.11.26 Supply Voltages
      27. 2.11.27 Ground Pins (VSS)
  3. 3Device Configurations
    1. 3.1 Control Module Registers
    2. 3.2 Boot Modes
      1. 3.2.1 XIP (NOR) Boot Options
      2. 3.2.2 NAND Flash Boot
      3. 3.2.3 NAND I2C Boot (I2C EEPROM)
      4. 3.2.4 MMC/SD Cards Boot
      5. 3.2.5 SPI Boot
      6. 3.2.6 Ethernet PHY Mode Selection
      7. 3.2.7 PCIe Bootmode (PCIE_32 and PCIE_64)
      8. 3.2.8 UART Bootmode
    3. 3.3 Pin Multiplexing Control
    4. 3.4 Handling Unused Pins
    5. 3.5 DeBugging Considerations
      1. 3.5.1 Pullup/Pulldown Resistors
  4. 4 System Interconnect
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)
    5. 5.5 Thermal Resistance Characteristics (PBGA Package) [CYE-04] (Thinner Top Hat)
  6. 6Power, Reset, Clocking, and Interrupts
    1. 6.1 Power, Reset and Clock Management (PRCM) Module
    2. 6.2 Power
      1. 6.2.1 Voltage and Power Domains
        1. 6.2.1.1 Core Logic Voltage Domains
        2. 6.2.1.2 Memory Voltage Domains
        3. 6.2.1.3 Power Domains
      2. 6.2.2 SmartReflex [Not Supported]
        1. 6.2.2.1 Dynamic Voltage Frequency Scaling (DVFS)
        2. 6.2.2.2 Adaptive Voltage Scaling [Not Supported]
      3. 6.2.3 Memory Power Management
      4. 6.2.4 SERDES_CLKP and SERDES_CLKN LDO
      5. 6.2.5 Dual Voltage I/Os
      6. 6.2.6 I/O Power-Down Modes
      7. 6.2.7 Standby Mode
      8. 6.2.8 Supply Sequencing
        1. 6.2.8.1 Power-Up Sequence
        2. 6.2.8.2 Power-Down Sequence
      9. 6.2.9 Power-Supply Decoupling
        1. 6.2.9.1 Analog and PLL
        2. 6.2.9.2 Digital
    3. 6.3 Reset
      1. 6.3.1  System-Level Reset Sources
      2. 6.3.2  Power-on Reset (POR pin)
      3. 6.3.3  External Warm Reset (RESET pin)
      4. 6.3.4  Emulation Warm Reset
      5. 6.3.5  Watchdog Reset
      6. 6.3.6  Software Global Cold Reset
      7. 6.3.7  Software Global Warm Reset
      8. 6.3.8  Test Reset (TRST pin)
      9. 6.3.9  Local Reset
      10. 6.3.10 Reset Priority
      11. 6.3.11 Reset Status Register
      12. 6.3.12 PCIE Reset Isolation
      13. 6.3.13 EMAC Switch Reset Isolation
      14. 6.3.14 RSTOUT_WD_OUT Pin
      15. 6.3.15 Effect of Reset on Emulation and Trace
      16. 6.3.16 Reset During Power Domain Switching
      17. 6.3.17 Pin Behaviors at Reset
      18. 6.3.18 Reset Electrical Data/Timing
    4. 6.4 Clocking
      1. 6.4.1  Device (DEV) and Auxiliary (AUX) Clock Inputs
        1. 6.4.1.1 Using the Internal Oscillators
        2. 6.4.1.2 Using a 1.8V LVCMOS-Compatible Clock Input
      2. 6.4.2  SERDES_CLKN/P Input Clock
      3. 6.4.3  AUD_CLKINx Input Clocks
      4. 6.4.4  CLKIN32 Input Clock
      5. 6.4.5  External Input Clocks
      6. 6.4.6  Output Clocks Select Logic
      7. 6.4.7  Input/Output Clocks Electrical Data/Timing
      8. 6.4.8  PLLs
        1. 6.4.8.1 PLL Power Supply Filtering
        2. 6.4.8.2 PLL Multipliers and Dividers
        3. 6.4.8.3 PLL Frequency Limits
        4. 6.4.8.4 PLL Register Descriptions
      9. 6.4.9  SYSCLKs
      10. 6.4.10 Module Clocks
    5. 6.5 Interrupts
      1. 6.5.1 ARM Cortex-A8 Interrupts
  7. 7 Peripheral Information and Timings
    1. 7.1  Parameter Information
      1. 7.1.1 1.8-V and 3.3-V Signal Transition Levels
      2. 7.1.2 3.3-V Signal Transition Rates
      3. 7.1.3 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  Controller Area Network Interface (DCAN)
      1. 7.3.1 DCAN Peripheral Register Descriptions
      2. 7.3.2 DCAN Electrical Data/Timing
    4. 7.4  EDMA
      1. 7.4.1 EDMA Channel Synchronization Events
      2. 7.4.2 EDMA Peripheral Register Descriptions
    5. 7.5  Emulation Features and Capability
      1. 7.5.1 Advanced Event Triggering (AET)
      2. 7.5.2 Trace
      3. 7.5.3 IEEE 1149.1 JTAG
        1. 7.5.3.1 JTAG ID (JTAGID) Register Description
        2. 7.5.3.2 JTAG Electrical Data/Timing
    6. 7.6  Ethernet MAC Switch (EMAC SW)
      1. 7.6.1 EMAC Peripheral Register Descriptions
      2. 7.6.2 EMAC Electrical Data/Timing
        1. 7.6.2.1 EMAC MII and GMII Electrical Data/Timing
        2. 7.6.2.2 EMAC RMII Electrical Data/Timing
        3. 7.6.2.3 EMAC RGMII Electrical Data/Timing
      3. 7.6.3 Management Data Input/Output (MDIO)
        1. 7.6.3.1 MDIO Peripheral Register Descriptions
        2. 7.6.3.2 MDIO Electrical Data/Timing
    7. 7.7  General-Purpose Input/Output (GPIO)
      1. 7.7.1 GPIO Peripheral Register Descriptions
      2. 7.7.2 GPIO Electrical Data/Timing
    8. 7.8  General-Purpose Memory Controller (GPMC) and Error Location Module (ELM)
      1. 7.8.1 GPMC and ELM Peripherals Register Descriptions
      2. 7.8.2 GPMC Electrical Data/Timing
        1. 7.8.2.1 GPMC/NOR Flash Interface Synchronous Mode Timing (Nonmultiplexed and Multiplexed Modes)
        2. 7.8.2.2 GPMC/NOR Flash Interface Asynchronous Mode Timing (Nonmultiplexed and Multiplexed Modes)
        3. 7.8.2.3 GPMC/NAND Flash and ELM Interface Timing
    9. 7.9  High-Definition Multimedia Interface (HDMI)
      1. 7.9.1 HDMI Design Guidelines
        1. 7.9.1.1 HDMI Interface Schematic
        2. 7.9.1.2 TMDS Routing
        3. 7.9.1.3 DDC Signals
        4. 7.9.1.4 HDMI ESD Protection Device (Required)
        5. 7.9.1.5 PCB Stackup Specifications
        6. 7.9.1.6 Grounding
    10. 7.10 High-Definition Video Processing Subsystem (HDVPSS)
      1. 7.10.1 HDVPSS Electrical Data/Timing
      2. 7.10.2 Video DAC Guidelines and Electrical Data/Timing
    11. 7.11 Inter-Integrated Circuit (I2C)
      1. 7.11.1 I2C Peripheral Register Descriptions
      2. 7.11.2 I2C Electrical Data/Timing
    12. 7.12 Imaging Subsystem (ISS)
      1. 7.12.1 ISSCAM Electrical Data/Timing
    13. 7.13 DDR2/DDR3 Memory Controller
      1. 7.13.1 DDR2/3 Memory Controller Register Descriptions
      2. 7.13.2 DDR2/DDR3 PHY Register Descriptions
      3. 7.13.3 DDR-Related Control Module Registers Description
      4. 7.13.4 DDR2/DDR3 Memory Controller Electrical Data/Timing
        1. 7.13.4.1 DDR2 Routing Specifications
          1. 7.13.4.1.1 DDR2 Interface
            1. 7.13.4.1.1.1  DDR2 Interface Schematic
            2. 7.13.4.1.1.2  Compatible JEDEC DDR2 Devices
            3. 7.13.4.1.1.3  PCB Stackup
            4. 7.13.4.1.1.4  Placement
            5. 7.13.4.1.1.5  DDR2 Keepout Region
            6. 7.13.4.1.1.6  Bulk Bypass Capacitors
            7. 7.13.4.1.1.7  High-Speed Bypass Capacitors
            8. 7.13.4.1.1.8  Net Classes
            9. 7.13.4.1.1.9  DDR2 Signal Termination
            10. 7.13.4.1.1.10 VREFSSTL_DDR Routing
          2. 7.13.4.1.2 DDR2 CK and ADDR_CTRL Routing
        2. 7.13.4.2 DDR3 Routing Specifications
          1. 7.13.4.2.1 DDR3 versus DDR2
          2. 7.13.4.2.2 DDR3 EMIFs
          3. 7.13.4.2.3 DDR3 Device Combinations
          4. 7.13.4.2.4 DDR3 Interface Schematic
            1. 7.13.4.2.4.1  Compatible JEDEC DDR3 Devices
            2. 7.13.4.2.4.2  PCB Stackup
            3. 7.13.4.2.4.3  Placement
            4. 7.13.4.2.4.4  DDR3 Keepout Region
            5. 7.13.4.2.4.5  Bulk Bypass Capacitors
            6. 7.13.4.2.4.6  High-Speed Bypass Capacitors
              1. 7.13.4.2.4.6.1 Return Current Bypass Capacitors and Vias
            7. 7.13.4.2.4.7  Net Classes
            8. 7.13.4.2.4.8  DDR3 Signal Termination
            9. 7.13.4.2.4.9  VREFSSTL_DDR Routing
            10. 7.13.4.2.4.10 VTT
            11. 7.13.4.2.4.11 CK and ADDR_CTRL Topologies and Routing Definition
              1. 7.13.4.2.4.11.1 Four DDR3 Devices
                1. 7.13.4.2.4.11.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
                2. 7.13.4.2.4.11.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
              2. 7.13.4.2.4.11.2 Two DDR3 Devices
                1. 7.13.4.2.4.11.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
                2. 7.13.4.2.4.11.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
              3. 7.13.4.2.4.11.3 One DDR3 Device
                1. 7.13.4.2.4.11.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
                2. 7.13.4.2.4.11.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
            12. 7.13.4.2.4.12 Data Topologies and Routing Definition
              1. 7.13.4.2.4.12.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
              2. 7.13.4.2.4.12.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
            13. 7.13.4.2.4.13 Routing Specification
              1. 7.13.4.2.4.13.1 CK and ADDR_CTRL Routing Specification
              2. 7.13.4.2.4.13.2 DQS and DQ Routing Specification
    14. 7.14 Multichannel Audio Serial Port (McASP)
      1. 7.14.1 McASP Device-Specific Information
      2. 7.14.2 McASP0, McASP1, McASP2, McASP3, McASP4, and McASP5 Peripheral Registers Descriptions
      3. 7.14.3 McASP (McASP[5:0]) Electrical Data/Timing
    15. 7.15 Multichannel Buffered Serial Port (McBSP)
      1. 7.15.1 McBSP Peripheral Register Descriptions
      2. 7.15.2 McBSP Electrical Data/Timing
    16. 7.16 MultiMedia Card/Secure Digital/Secure Digital Input Output (MMC/SD/SDIO)
      1. 7.16.1 MMC/SD/SDIO Peripheral Register Descriptions
      2. 7.16.2 MMC/SD/SDIO Electrical Data/Timing
    17. 7.17 Peripheral Component Interconnect Express (PCIe)
      1. 7.17.1 PCIe Peripheral Register Descriptions
      2. 7.17.2 PCIe Electrical Data/Timing
      3. 7.17.3 PCIe Design and Layout Guidelines
        1. 7.17.3.1 Clock Source
        2. 7.17.3.2 PCIe Connections and Interface Compliance
          1. 7.17.3.2.1 Coupling Capacitors
          2. 7.17.3.2.2 Polarity Inversion
        3. 7.17.3.3 Nonstandard PCIe Connections
          1. 7.17.3.3.1 PCB Stackup Specifications
          2. 7.17.3.3.2 Routing Specifications
    18. 7.18 Serial ATA Controller (SATA)
      1. 7.18.1 SATA Peripheral Register Descriptions
      2. 7.18.2 SATA Interface Design Guidelines
        1. 7.18.2.1 SATA Interface Schematic
        2. 7.18.2.2 Compatible SATA Components and Modes
        3. 7.18.2.3 PCB Stackup Specifications
        4. 7.18.2.4 Routing Specifications
        5. 7.18.2.5 Coupling Capacitors
    19. 7.19 Serial Peripheral Interface (SPI)
      1. 7.19.1 SPI Peripheral Register Descriptions
      2. 7.19.2 SPI Electrical Data/Timing
    20. 7.20 Timers
      1. 7.20.1 Timer Peripheral Register Descriptions
      2. 7.20.2 Timer Electrical/Data Timing
    21. 7.21 Universal Asynchronous Receiver/Transmitter (UART)
      1. 7.21.1 UART Peripheral Register Descriptions
      2. 7.21.2 UART Electrical/Data Timing
    22. 7.22 Universal Serial Bus (USB2.0)
      1. 7.22.1 USB2.0 Peripheral Register Descriptions
      2. 7.22.2 USB2.0 Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device and Development-Support Tool Nomenclature
    2. 8.2 Documentation Support
    3. 8.3 Related Links
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Export Control Notice
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CYE|684
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Device Configurations

3.1 Control Module Registers

3.2 Boot Modes

The state of the device after boot is determined by sampling the input states of the BTMODE[15:0] pins when device reset (POR or RESET) is deasserted. The sampled values are latched into the CONTROL_STATUS register, which is part of the Control Module. The BTMODE[15:11] values determine the following system boot settings:

  • RSTOUT_WD_OUT Control
  • GPMC CS0 Default Data Bus Width, Wait Enable, and Address/Data Multiplexing

For additional details on BTMODE[15:11] pin functions, see Table 2-1, Boot Configuration Terminal Functions.

The BTMODE[4:0] values determine the boot mode order according to Table 3-1, Boot Mode Order. The 1st boot mode listed for each BTMODE[4:0] configuration is executed as the primary boot mode. If the primary boot mode fails, the 2nd, 3rd, and 4th boot modes are executed in that order until a successful boot is completed.

The BTMODE[7:5] pins are RESERVED and should be pulled down as indicated inTable 2-1, Boot Configuration Terminal Functions.

When the EMAC bootmode is selected (see Table 3-1), the sampled value from BTMODE[9:8] pins are used to determine the Ethernet PHY Mode selection (see Table 3-7).

When the XIP (MUX0), XIP (MUX1), XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode is selected (see Table 3-1), the sampled value from BTMODE[10] pin is used to select between GPMC pin muxing options shown in Table 3-2, XIP (on GPMC) Boot Options [Muxed or Non-Muxed].

For more detailed information on booting the device, see the ROM Code Memory and Peripheral Booting chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).

Table 3-1 Boot Mode Order

BTMODE[4:0] 1st 2nd 3rd 4th
00000 RESERVED RESERVED RESERVED RESERVED
00001 UART XIP w/WAIT (MUX0)(1)(3) MMC SPI
00010 UART SPI NAND NANDI2C
00011 UART SPI XIP (MUX0)(1)(3) MMC
00100 EMAC(2) SPI NAND NANDI2C
00101 RESERVED RESERVED RESERVED RESERVED
00110 RESERVED RESERVED RESERVED RESERVED
00111 EMAC(2) MMC SPI XIP (MUX1)(1)(3)
01000 PCIE_32(4) RESERVED RESERVED RESERVED
01001 PCIE_64(4) RESERVED RESERVED RESERVED
01010 RESERVED RESERVED RESERVED RESERVED
01011 RESERVED RESERVED RESERVED RESERVED
01100 RESERVED RESERVED RESERVED RESERVED
01101 RESERVED RESERVED RESERVED RESERVED
01110 RESERVED RESERVED RESERVED RESERVED
01111 Fast XIP (MUX0)(1) UART EMAC(2) PCIE_64(4)
10000 XIP (MUX1)(1)(3) UART EMAC(2) MMC
10001 XIP w/WAIT (MUX1)(1)(3) UART EMAC(2) MMC
10010 NAND NANDI2C SPI UART
10011 NAND NANDI2C MMC UART
10100 NAND NANDI2C SPI EMAC(2)
10101 NANDI2C MMC EMAC(2) UART
10110 SPI MMC UART EMAC(2)
10111 MMC SPI UART EMAC(2)
11000 SPI MMC PCIE_32(4) RESERVED
11001 SPI MMC PCIE_64(4) RESERVED
11010 XIP (MUX0)(1)(3) UART SPI MMC
11011 XIP w/WAIT (MUX0)(1)(3) UART SPI MMC
11100 RESERVED RESERVED RESERVED RESERVED
11101 RESERVED RESERVED RESERVED RESERVED
11110 RESERVED RESERVED RESERVED RESERVED
11111 Fast XIP (MUX0)(1) EMAC(2) UART PCIE_32(4)
(1) GPMC CS0 eXecute In Place (XIP) boot for NOR/OneNAND/ROM. MUX0/1 refers to the multiplexing option for the GPMC_A[12:0] pins. For more detailed information on booting the device, including which pins are used for each boot mode, see the ROM Code Memory and Peripheral Booting chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).
(2) When the EMAC bootmode is selected, the sampled value from BTMODE[9:8] pins are used to determine the Ethernet PHY Mode Selection (see Table 3-7).
(3) When the XIP (MUX0), XIP (MUX1), XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode is selected, the sampled value from BTMODE[10] pin is used to select between GPMC pin configuration options shown in Table 3-2, XIP (on GPMC) Boot Options.
(4) When the PCIe bootmode is selected (PCIE_32 or PCI_64), the sampled value from BTMODE[15:12] pins are used to determine the addressing options. For more detailed information on the PCIe addressing options, see the ROM Code Memory and Peripheral Booting chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).

3.2.1 XIP (NOR) Boot Options

Table 3-2 shows the XIP (NOR) boot mode GPMC pin configuration options (Option A: BTMODE[10] = 0 and Option B: BTMODE[10] = 1). For Option B, the pull state on select pins is reconfigured to IPD and remains IPD after boot until the user software reconfigures it.

Table 3-2 XIP (on GPMC) Boot Options

SIGNAL NAME PIN NO. OTHER CONDITIONS CONTROLLED I/O FUNCTION DURING XIP (NOR) BOOT
BTMODE[10] = 0 [OPTION A] BTMODE[10] = 1 [OPTION B]
PIN FUNCTION PULL
STATE		 PIN FUNCTION PULL
STATE
GPMC_CS[0]/* T28 GPMC_CS[0] IPU GPMC_CS[0] IPU
GPMC_ADV_ALE/* M26 BTMODE[14:13] = 01b or 10b (Mux) GPMC_ADV_ALE IPU GPMC_ADV_ALE IPU
BTMODE[14:13] = 00b (Non-Mux) Default
GPMC_OE_RE T27 GPMC_OE_RE IPU GPMC_OE_RE IPU
GPMC_BE[0]_CLE/GPMC_A[25]/* U27 GPMC_BE[0]_CLE IPD Default IPD
GPMC_BE[1]/GPMC_A[24]/* V28 Default IPD Default IPD
GPMC_WE U28 GPMC_WE IPU GPMC_WE IPU
GPMC_WAIT[0]/GPMC_A[26]/* W28 BTMODE[15] = 1b (WAIT Used/Enabled) GPMC_WAIT[0] IPU GPMC_WAIT[0] IPU
BTMODE[15] = 0b (WAIT Not Used/Disabled) Default IPD(1)
GPMC_CLK/* R26 GPMC_CLK IPU Default IPU
GPMC_D[15:0]/* Y25,V24,U23,U24,AA27,Y26,AB28,Y27,V25,U25,AA28,V26,W27,V27,Y28,U26 GPMC_D[15:0] Off GPMC_D[15:0] Off
*/GPMC_A[27]/GPMC_A[26]/GPMC_A[0]/* J25 BTMODE[12] = 0b (8-bit Mode) GPMC_A[0] IPD GPMC_A[0] IPD
BTMODE[12] = 1b (16-bit Mode) Default
*/GPMC_A[1:12]/* (M0) T23,H26,F28,G27,K22,K23,J24,H25,H22,H23,G23,F27 XIP_MUX0 Mode GPMC_A[1:12] IPD GPMC_A[1:12] IPD
XIP_MUX1 Mode Default IPD Default IPD
*/GPMC_A[1:12]/* (M1) J28,K27,M24,L26,AD18,AC18,AC19,AA22,AE23,AD23,AB23,AF18 XIP_MUX0 Mode Default Default Default Default
XIP_MUX1 Mode GPMC_A[1:12] Default GPMC_A[1:12] Default
*/GPMC_A[13:15]/* (M0) J22,H24,J23 Default IPD Default IPD
*/GPMC_A[0]/* (M1) AF28 BTMODE[12] = 0b (8-bit Mode) Default IPU Default IPU
BTMODE[12] = 1b (16-bit Mode)
*/GPMC_A[13]/* (M1) AF27 BTMODE[14:13] = 01b or 10b (Mux) Default IPU Default IPU
BTMODE[14:13] = 00b (Non-Mux) IPD(1)
*/GPMC_A[14]/* (M1) AG28 BTMODE[14:13] = 01b or 10b (Mux) Default IPU Default IPU
BTMODE[14:13] = 00b (Non-Mux) IPD(1)
*/GPMC_A[15]/* (M1) AE27 Default IPD Default IPD
GPMC_A[16:19]/* AD27,V23,AE28,AC27 Default IPD Default IPD
GPMC_A[20] (M0) AD28 Default IPU Default IPD(1)
GPMC_A[21] (M0) AC28 Default IPD Default IPD
GPMC_A[22] (M0) AB27 Default IPU Default IPD(1)
GPMC_A[23] (M0) AA26 Default IPD Default IPD
*/GPMC_A[24]/GPMC_A[20]/* L25 Default IPU Default IPD(1)
*/GPMC_A[25]/GPMC_A[21]/* N23 Default IPU Default IPD(1)
*/GPMC_A[26]/GPMC_A[22]/* P22 Default IPU Default IPD(1)
*/GPMC_A[27]/GPMC_A[23]/* R24 Default IPU Default IPU
GPMC_A[24] (M1) M25 Default IPU Default IPU
GPMC_A[25] (M1) K28 Default IPU Default IPU
(1) After initial power-up the internal pullup (IPU) will be at its default configuration of IPU. During the boot ROM execution, the pull state is reconfigured to IPD and it remains IPD after boot until the user software reconfigures it.

3.2.2 NAND Flash Boot

Table 3-3 lists the device pins that are configured by the ROM for the NAND Flash boot mode.

NOTE: Table 3-3 lists the configuration of the GPMC_CLK pin (pin mux and pull state) in NAND bootmodes.

The NAND flash memory is not XIP and requires shadowing before the code can be executed.

Table 3-3 Pins Used in NAND FLASH Bootmode

SIGNAL NAME PIN NO. TYPE OTHER CONDITIONS
GPMC_CS[0]/* T28 O BTMODE[12] = 0b (8-bit Mode)
BTMODE[12] = 1b (16-bit Mode)

BTMODE[14:13] = 00b (GPMC CS0 not muxed)

BTMODE[15] = 0b (wait disabled)
GPMC_ADV_ALE/* M26 O
GPMC_OE_RE T27 O
GPMC_BE[0]_CLE/GPMC_A[25]/* U27 O
GPMC_BE[1]/GPMC_A[24]/* V28 O
GPMC_WE U28 O
GPMC_WAIT[0]/GPMC_A[26]/*(1) W28 I
GPMC_CLK/* R26 O
GPMC_D[15:0]/* Y25,V24,U23,U24,AA27,Y26,AB28,Y27,
V25,U25,AA28,V26,W27,V27,Y28,U26		 I/O
(1) GPMC_CLK/* is not configured in BTMODE[10] = 1 [OPTION B]

3.2.3 NAND I2C Boot (I2C EEPROM)

Table 3-4 lists the device pins that are configured by the ROM for the NAND I2C boot mode.

Table 3-4 Pins Used in NAND I2C Bootmode

SIGNAL NAME PIN NO. TYPE
I2C[0]_SCL AC4 I/O
I2C[0]_SDA AB6 I/O

3.2.4 MMC/SD Cards Boot

Table 3-5 lists the device pins that are configured by the ROM for the MMC/SD boot mode.

Table 3-5 Pins Used in MMC/SD Bootmode

SIGNAL NAME PIN NO. TYPE
SD1_CLK P3 O
SD1_CMD/GP0[0] [MUX0] P2 O
SD1_DAT[0] P1 I/O
SD1_DAT[1]_SDIRQ P5 I/O
SD_DAT[2]_SDRW P4 I/O
SD1_DAT[3] P6 I/O

3.2.5 SPI Boot

Table 3-6 lists the device pins that are configured by the ROM for the SPI boot mode.

Table 3-6 Pins Used in SPI Bootmode

SIGNAL NAME PIN NO. TYPE
SPI[0]_SCS[0] AD6 I/O
SPI[0]_D[0] (MISO) AE3 I/O
SPI[0]_D[1] (MOSI) AF3 I/O
SPI[0]_SCLK AC7 I/O

3.2.6 Ethernet PHY Mode Selection

When the EMAC bootmode is selected, via the BTMODE[4:0] pins (see Table 3-1), Table 3-7 shows the sampled value of BTMODE[9:8] pins and the Ethernet PHY Mode selection.

Table 3-8 shows the signal names (pin functions) and the associated pin numbers selected in each particular EMAC mode.

Table 3-7 EMAC PHY Mode Selection

BTMODE[9:8] ETHERNET PHY MODE SELECTION
00b MII
01b RMII
10b RGMII
11b RESERVED

Table 3-8 Pins Used in EMAC[0] MII/GMII, RGMII, and RMII Boot Modes

PIN NO. SIGNAL NAMES
MII/GMII TYPE RGMII TYPE RMII TYPE
J27 DEFAULT DEFAULT EMAC_RMREFCLK Output only
L23 EMAC[0]_MCOL I EMAC[0]_RGRXCTL I EMAC[0]_RMRXD[0] I
R25 EMAC[0]_MCRS I EMAC[0]_RGRXD[2] I EMAC[0]_RMRXD[1] I
K23 EMAC[0]_GMTCLK O DEFAULT DEFAULT
H27 EMAC[0]_MRCLK I EMAC[0]_RGTXC O EMC[0]_RMCRSDV I
G28 EMAC[0]_MRXD[0] I EMAC[0]_RGTXD[0] O EMAC[0]_RMTXD[0] O
P23 EMAC[0]_MRXD[1] I EMAC[0]_RGRXD[0] I EMAC[0]_RMTXD[1] O
R23 EMAC[0]_MRXD[2] I EMAC[0]_RGRXD[1] I EMAC[0]_RMTXEN O
J25 EMAC[0]_MRXD[3] I DEFAULT DEFAULT
T23 EMAC[0]_MRXD[4] I EMAC[0]_RGRXD[3] I DEFAULT
H26 EMAC[0]_MRXD[5] I EMAC[0]_RGTXD[3] O DEFAULT
F28 EMAC[0]_MRXD[6] I EMAC[0]_RGTXD[2] O DEFAULT
G27 EMAC[0]_MRXD[7] I EMAC[0]_RGTXD[1] O DEFAULT
K22 EMAC[0]_MRXDV I DEFAULT DEFAULT
J26 EMAC[0]_MRXER I EMAC[0]_RGTXCTL O EMAC[0]_RMRXER I
L24 EMAC[0]_MTCLK I EMAC[0]_RGRXC I DEFAULT
J24 EMAC[0]_MTXD[0] O DEFAULT DEFAULT
H25 EMAC[0]_MTXD[1] O DEFAULT DEFAULT
H22 EMAC[0]_MTXD[2] O DEFAULT DEFAULT
H23 EMAC[0]_MTXD[3] O DEFAULT DEFAULT
G23 EMAC[0]_MTXD[4] O DEFAULT DEFAULT
F27 EMAC[0]_MTXD[5] O DEFAULT DEFAULT
J22 EMAC[0]_MTXD[6] O DEFAULT DEFAULT
H24 EMAC[0]_MTXD[7] O DEFAULT DEFAULT
J23 EMAC[0]_MTXEN O DEFAULT DEFAULT
H28 MDCLK O MDCLK O MDCLK O
P24 MDIO I/O MDIO I/O MDIO I/O

3.2.7 PCIe Bootmode (PCIE_32 and PCIE_64)

Table 3-9 lists the device pins that are configured by the ROM for the PCIe boot mode.

Table 3-9 Pins Used in PCIe Bootmode

SIGNAL NAME PIN NO. TYPE
PCIE_TXP0 AD2 O
PCIE_TXN0 AD1 O
PCIE_RXP0 AC2 I
PCIE_RXN0 AC1 I
SERDES_CLKIP AF1 I
SERDES_CLKN AF2 I

3.2.8 UART Bootmode

Table 3-10 lists the device pins that are configured by the ROM for the UART boot mode.

Table 3-10 Pins Used in UART Bootmode

SIGNAL NAME PIN NO. TYPE
UART0_RXD AH5 I
UART0_TXD AG5 O

3.3 Pin Multiplexing Control

Device level pin multiplexing is controlled on a pin-by-pin basis by the MUXMODE bits of the PINCNTL1 – PINCNTL270 registers in the Control Module.

Pin multiplexing selects which one of several peripheral pin functions controls the pin's I/O buffer output data values. Table 3-11 shows the peripheral pin functions associated with each MUXMODE setting for all multiplexed pins. The default pin multiplexing control for almost every pin is to select MUXMODE = 0x0, in which case the pin's I/O buffer is 3-stated.

In most cases, the input from each pin is routed to all of the peripherals that share the pin, regardless of the MUXMODE setting. However, in some cases a constant "0" or "1" value is routed to the associated peripheral when its peripheral function is not selected to control any output pin. For more details on the De-Selected Input State (DSIS), see the "MUXED" columns of each Terminal Functions table (Section 2.11, Terminal Functions).

Some peripheral pin functions can be routed to more than one device pin. These types of peripheral pin functions are called Multimuxed (MM) and may have different Switching Characteristics and Timing Requirements for each device pin option. The Multimuxed peripheral pin functions are labeled as "MM" in Terminal Functions tables in Section 2.11, Terminal Functions and the associated timings for each MM pin option are in Section 7, Peripheral Information and Timings.

For more detailed information on the Pin Control 1 through Pin Control 270 (PINCNTLx) registers breakout, see Figure 3-1 and Table 3-11. For the register reset values of each PINCNTLx register, see Table 3-13, PINCNTLx Registers MUXMODE Functions.

Figure 3-1 PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Breakout
31 24 23 20 19 18 17 16
RESERVED RESERVED RSV RXACTIVE PLLTYPESEL PLLUDEN
R - 0000 0000 R - 0000 R/W (see Table 3-13 for register reset value)
15 8 7 0
RESERVED MUXMODE[7:0] (see Table 3-13)
R - 0000 0000 R/W - 0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3-11 PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Bit Descriptions

Bit Field Description Comments
31:20 RESERVED Reserved. Read only, writes have no effect. For PINCNTLx register reset value examples, see Table 3-12, PNICNTLx Register Reset Value Examples.

For the full register reset values of all PINCNTLx registers, see Table 3-13, PINCNTLx Registers MUXMODE Functions.
19 RSV Reserved. This bit must always be written with the reset (default) value.
(See Table 3-13 for full register reset value)
18 RXACTIVE Receiver Enable

0 = Receiver Disabled
1 = Receiver Enabled
17 PLLTYPSEL Pullup/Pulldown Type Selection bit

0 = Pulldown (PD) selected
1 = Pullup (PU) selected
16 PLLUDEN Pullup/Pulldown Enable bit

0 = PU/PD enabled
1 = PU/PD disabled
15:8 RESERVED Reserved. Read only, writes have no effect.
7:0 MUXMODE[7:0] MUXMODE Selection bits

These bits select the multiplexed mode pin function settings (seeTable 3-13, PINCNTLx Registers MUXMODE Functions). A value of zero results in the pin being tri-stated. Nonzero values other than those shown in Table 3-13 are Reserved.

Table 3-12 PINCNTLx Register Reset Value Examples

HEX
ADDRESS
RANGE		 PINCNTLx
REGISTER
NAME		 Bits 31:24 Bits 23:20 Bit 19 Bit 18 Bit 17 Bit 16 Bits 15:8 Bits 7:0 REGISTER
RESET
VALUE
RESERVED RESERVED RSV RSV PLLTYPESEL PLLUDEN RESERVED MUXMODE[7:0]
0x4814 0800 PINCNTL1 00h 0h 0 1 1 0 00h 00h 0x0006 0000
0x4814 0804 PINCNTL2 00h 0h 1 1 1 0 00h 00h 0x000E 0000
0x4814 0808 PINCNTL3 00h 0h 1 1 1 0 00h 00h 0x000E 0000
…
0x4814 0C34 PINCNTL270 00h 0h 1 1 0 0 00h 00h 0x000C 0000

 

  1. "(M0)" represents multimuxed option "0" for this pin function, "(M1)" represents multimuxed option "1" for this pin function, ... etc.
  2. Within this MUXMODE setting, EMAC[x] GMII or RGMII pin functions are selected via the RGMII0_EN and/or RGMII1_EN bits (8 and 9, respectively) in the GMII_SEL register [0x4814_0650] of the Control Module. "0" = GMII (default) and "1" = RGMII.

Table 3-13 PINCNTLx Registers MUXMODE Functions

HEX
ADDRESS		 REGISTER
NAME		 PIN
NO.		 REGISTER
RESET
VALUE		 MUXMODE[7:0] SETTINGS
0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80
0x4814 0800 PINCNTL1 P3 0x0006 0000 SD1_CLK
0x4814 0804 PINCNTL2 P2 0x000E 0000 SD1_CMD(M0) GP0[0]
0x4814 0808 PINCNTL3 P1 0x000E 0000 SD1_DAT[0]
0x4814 080C PINCNTL4 P5 0x000E 0000 SD1_DAT[1]_SDIRQ
0x4814 0810 PINCNTL5 P4 0x000E 0000 SD1_DAT[2]_SDRW
0x4814 0814 PINCNTL6 P6 0x000E 0000 SD1_DAT[3]
0x4814 0818 PINCNTL7 W6 0x000E 0000 DEVOSC_WAKE SPI[1]_SCS[1] TIM5_IO(M1) GP1[7](M0)
0x4814 081C PINCNTL8 Y6 0x0006 0000 SD0_CLK GP0[1]
0x4814 0820 PINCNTL9 N1 0x000E 0000 SD0_CMD SD1_CMD(M1) GP0[2]
0x4814 0824 PINCNTL10 R7 0x000E 0000 SD0_DAT[0] SD1_DAT[4] GP0[3]
0x4814 0828 PINCNTL11 Y5 0x000E 0000 SD0_DAT[1]_SDIRQ SD1_DAT[5] GP0[4]
0x4814 082C PINCNTL12 Y3 0x000E 0000 SD0_DAT[2]_SDRW SD1_DAT[6] GP0[5]
0x4814 0830 PINCNTL13 Y4 0x000E 0000 SD0_DAT[3] SD1_DAT[7] GP0[6]
0x4814 0834 PINCNTL14 L5 0x000C 0000 AUD_CLKIN0 MCA[0]_AXR[7](M1) MCA[0]_AHCLKX MCA[3]_AHCLKX USB1_DRVVBUS
0x4814 0838 PINCNTL15 R5 0x000C 0000 AUD_CLKIN1 MCA[0]_AXR[8](M1) MCA[1]_AHCLKX MCA[4]_AHCLKX EDMA_EVT3(M1) TIM2_IO(M1) GP0[8]
0x4814 083C PINCNTL16 H1 0x000C 0000 AUD_CLKIN2 MCA[0]_AXR[9](M1) MCA[2]_AHCLKX MCA[5]_AHCLKX EDMA_EVT2(M1) TIM3_IO(M1) GP0[9]
0x4814 0840 PINCNTL17 R4 0x0004 0000 MCA[0]_ACLKX
0x4814 0844 PINCNTL18 L3 0x000C 0000 MCA[0]_AFSX
0x4814 0848 PINCNTL19 K2 0x0004 0000 MCA[0]_ACLKR MCA[5]_AXR[2]
0x4814 084C PINCNTL20 K1 0x000C 0000 MCA[0]_AFSR MCA[5]_AXR[3]
0x4814 0850 PINCNTL21 J2 0x000C 0000 MCA[0]_AXR[0]
0x4814 0854 PINCNTL22 J1 0x000E 0000 MCA[0]_AXR[1] I2C[3]_SCL(M0)
0x4814 0858 PINCNTL23 L4 0x000E 0000 MCA[0]_AXR[2] I2C[3]_SDA(M0)
0x4814 085C PINCNTL24 M5 0x000C 0000 MCA[0]_AXR[3]
0x4814 0860 PINCNTL25 R6 0x000C 0000 MCA[0]_AXR[4] MCA[1]_AXR[8](M0)
0x4814 0864 PINCNTL26 M3 0x000C 0000 MCA[0]_AXR[5] MCA[1]_AXR[9](M0)
0x4814 0868 PINCNTL27 M4 0x000C 0000 MCA[0]_AXR[6] MCB_DR
0x4814 086C PINCNTL28 L2 0x000C 0000 MCA[0]_AXR[7](M0) MCB_DX
0x4814 0870 PINCNTL29 L1 0x000C 0000 MCA[0]_AXR[8](M0) MCB_FSX MCB_FSR(M1)
0x4814 0874 PINCNTL30 M6 0x000C 0000 MCA[0]_AXR[9](M0) MCB_CLKX MCB_CLKR(M1)
0x4814 0878 PINCNTL31 U5 0x0004 0000 MCA[1]_ACLKX
0x4814 087C PINCNTL32 V3 0x000C 0000 MCA[1]_AFSX
0x4814 0880 PINCNTL33 M1 0x0004 0000 MCA[1]_ACLKR MCA[1]_AXR[4]
0x4814 0884 PINCNTL34 M2 0x000C 0000 MCA[1]_AFSR MCA[1]_AXR[5]
0x4814 0888 PINCNTL35 V4 0x000E 0000 MCA[1]_AXR[0] SD0_DAT[4]
0x4814 088C PINCNTL36 T6 0x000E 0000 MCA[1]_AXR[1] SD0_DAT[5]
0x4814 0890 PINCNTL37 R3 0x000C 0000 MCA[1]_AXR[2] MCB_FSR(M0)
0x4814 0894 PINCNTL38 N6 0x000C 0000 MCA[1]_AXR[3] MCB_CLKR(M0)
0x4814 0898 PINCNTL39 U6 0x0006 0000 MCA[2]_ACLKX GP0[10](M1)
0x4814 089C PINCNTL40 AA5 0x000E 0000 MCA[2]_AFSX GP0[11](M1)
0x4814 08A0 PINCNTL41 N2 0x000E 0000 MCA[2]_AXR[0] SD0_DAT[6] UART5_RXD(M3) GP0[12](M1)
0x4814 08A4 PINCNTL42 V6 0x000E 0000 MCA[2]_AXR[1] SD0_DAT[7] UART5_TXD(M3) GP0[13](M1)
0x4814 08A8 PINCNTL43 V5 0x000C 0000 MCA[2]_AXR[2] MCA[1]_AXR[6] TIM2_IO(M0) GP0[14](M1)
0x4814 08AC PINCNTL44 H2 0x000C 0000 MCA[2]_AXR[3] MCA[1]_AXR[7] TIM3_IO(M0) GP0[15](M1)
0x4814 08B0 PINCNTL45 G6 0x0004 0000 MCA[3]_ACLKX GP0[16](M1)
0x4814 08B4 PINCNTL46 H4 0x000C 0000 MCA[3]_AFSX GP0[17](M1)
0x4814 08B8 PINCNTL47 G1 0x000C 0000 MCA[3]_AXR[0] TIM4_IO(M0) GP0[18](M1)
0x4814 08BC PINCNTL48 G2 0x000C 0000 MCA[3]_AXR[1] TIM5_IO(M0) GP0[19](M1)
0x4814 08C0 PINCNTL49 F2 0x000C 0000 MCA[3]_AXR[2] MCA[1]_AXR[8](M1) GP0[20](M1)
0x4814 08C4 PINCNTL50 J6 0x000C 0000 MCA[3]_AXR[3] MCA[1]_AXR[9](M1)
0x4814 08C8 PINCNTL51 K7 0x0004 0000 MCA[4]_ACLKX GP0[21](M1)
0x4814 08CC PINCNTL52 H3 0x000C 0000 MCA[4]_AFSX GP0[22](M1)
0x4814 08D0 PINCNTL53 H6 0x000C 0000 MCA[4]_AXR[0] GP0[23](M1)
0x4814 08D4 PINCNTL54 J4 0x000C 0000 MCA[4]_AXR[1] TIM6_IO(M0) GP0[24](M1)
0x4814 08D8 PINCNTL55 J3 0x000C 0000 MCA[5]_ACLKX GP0[25](M1)
0x4814 08DC PINCNTL56 H5 0x000C 0000 MCA[5]_AFSX GP0[26](M1)
0x4814 08E0 PINCNTL57 L7 0x000C 0000 MCA[5]_AXR[0] MCA[4]_AXR[2] GP0[27](M1)
0x4814 08E4 PINCNTL58 L6 0x000C 0000 MCA[5]_AXR[1] MCA[4]_AXR[3] TIM7_IO(M0) GP0[28](M1)
0x4814 08E8 PINCNTL59 U4 0x0004 0000 UART2_RXD(M1) GP0[29]
0x4814 08EC PINCNTL60 T2 0x0004 0000 TCLKIN GP0[30]
0x4814 08F0 PINCNTL61 U3 0x000C 0000 UART2_TXD(M1) GP0[31]
0x4814 08F4 PINCNTL62 W1 0x000C 0000 GP1[7](M1)
0x4814 08F8 PINCNTL63 W2 0x000E 0000 GP1[8](M1)
0x4814 08FC PINCNTL64 V1 0x000C 0000 GP1[9](M1)
0x4814 0900 PINCNTL65 V2 0x000E 0000 GP1[10](M1)
0x4814 0904 PINCNTL66 – 0x000C 0000 Reserved. Do Not Program this Register.
0x4814 0908 PINCNTL67 – 0x000E 0000 Reserved. Do Not Program this Register.
0x4814 090C PINCNTL68 AH6 0x000E 0000 DCAN0_TX UART2_TXD(M2) I2C[3]_SDA(M1) GP1[0]
0x4814 0910 PINCNTL69 AG6 0x000E 0000 DCAN0_RX UART2_RXD(M2) I2C[3]_SCL(M1) GP1[1]
0x4814 0914 PINCNTL70 AH5 0x000E 0000 UART0_RXD
0x4814 0918 PINCNTL71 AG5 0x000E 0000 UART0_TXD
0x4814 091C PINCNTL72 AE6 0x000E 0000 UART0_CTS UART4_RXD(M3) DCAN1_TX SPI[1]_SCS[3] SD0_SDCD
0x4814 0920 PINCNTL73 AF5 0x000E 0000 UART0_RTS UART4_TXD(M3) DCAN1_RX SPI[1]_SCS[2] SD2_SDCD
0x4814 0924 PINCNTL74 AH4 0x000E 0000 UART0_DCD UART3_RXD(M0) SPI[0]_SCS[3] I2C[2]_SCL(M0) SD1_POW GP1[2]
0x4814 0928 PINCNTL75 AG4 0x000E 0000 UART0_DSR UART3_TXD(M0) SPI[0]_SCS[2] I2C[2]_SDA(M0) SD1_SDWP GP1[3]
0x4814 092C PINCNTL76 AG2 0x000E 0000 UART0_DTR UART3_CTS(M0) UART1_TXD(M0) GP1[4]
0x4814 0930 PINCNTL77 AF4 0x000E 0000 UART0_RIN UART3_RTS(M0) UART1_RXD(M0) GP1[5]
0x4814 0934 PINCNTL78 AF24 0x000E 0000 I2C[1]_SCL HDMI_SCL(M0)
0x4814 0938 PINCNTL79 AG24 0x000E 0000 I2C[1]_SDA HDMI_SDA(M0)
0x4814 093C PINCNTL80 AE5 0x0006 0000 SPI[0]_SCS[1] SD1_SDCD SATA_ACT0_LED EDMA_EVT1(M1) TIM4_IO(M1) GP1[6]
0x4814 0940 PINCNTL81 AD6 0x0006 0000 SPI[0]_SCS[0]
0x4814 0944 PINCNTL82 AC7 0x0006 0000 SPI[0]_SCLK
0x4814 0948 PINCNTL83 AF3 0x0006 0000 SPI[0]_D[1]
0x4814 094C PINCNTL84 AE3 0x0006 0000 SPI[0]_D[0]
0x4814 0950 PINCNTL85 AD3 0x0006 0000 SPI[1]_SCS[0] GP1[16](M1)
0x4814 0954 PINCNTL86 AC3 0x0006 0000 SPI[1]_SCLK GP1[17](M1)
0x4814 0958 PINCNTL87 AA3 0x0006 0000 SPI[1]_D[1] GP1[18](M1)
0x4814 095C PINCNTL88 AA6 0x0006 0000 SPI[1]_D[0] GP1[26](M1)
0x4814 0960 PINCNTL89 U26 0x0005 0000 GPMC_D[0] BTMODE[0]
0x4814 0964 PINCNTL90 Y28 0x0005 0000 GPMC_D[1] BTMODE[1]
0x4814 0968 PINCNTL91 V27 0x0005 0000 GPMC_D[2] BTMODE[2]
0x4814 096C PINCNTL92 W27 0x0005 0000 GPMC_D[3] BTMODE[3]
0x4814 0970 PINCNTL93 V26 0x0005 0000 GPMC_D[4] BTMODE[4]
0x4814 0974 PINCNTL94 AA28 0x0005 0000 GPMC_D[5] BTMODE[5]
0x4814 0978 PINCNTL95 U25 0x0005 0000 GPMC_D[6] BTMODE[6]
0x4814 097C PINCNTL96 V25 0x0005 0000 GPMC_D[7] BTMODE[7]
0x4814 0980 PINCNTL97 Y27 0x0005 0000 GPMC_D[8] BTMODE[8]
0x4814 0984 PINCNTL98 AB28 0x0005 0000 GPMC_D[9] BTMODE[9]
0x4814 0988 PINCNTL99 Y26 0x0005 0000 GPMC_D[10] BTMODE[10]
0x4814 098C PINCNTL100 AA27 0x0005 0000 GPMC_D[11] BTMODE[11]
0x4814 0990 PINCNTL101 U24 0x0005 0000 GPMC_D[12] BTMODE[12]
0x4814 0994 PINCNTL102 U23 0x0005 0000 GPMC_D[13] BTMODE[13]
0x4814 0998 PINCNTL103 V24 0x0005 0000 GPMC_D[14] BTMODE[14]
0x4814 099C PINCNTL104 Y25 0x0005 0000 GPMC_D[15] BTMODE[15]
0x4814 09A0 PINCNTL105 AD27 0x0004 0000 GPMC_A[16] GP2[5](M0)
0x4814 09A4 PINCNTL106 V23 0x0004 0000 GPMC_A[17] GP2[6](M0)
0x4814 09A8 PINCNTL107 AE28 0x0004 0000 GPMC_A[18] TIM2_IO(M2) GP1[13](M0)
0x4814 09AC PINCNTL108 AC27 0x0004 0000 GPMC_A[19] TIM3_IO(M2) GP1[14](M0)
0x4814 09B0 PINCNTL109 AD28 0x0006 0000 GPMC_A[20](M0) SPI[2]_SCS[1] GP1[15](M0)
0x4814 09B4 PINCNTL110 AC28 0x0004 0000 GPMC_A[21](M0) SPI[2]_D[0](M0) GP1[16](M0)
0x4814 09B8 PINCNTL111 AB27 0x0006 0000 GPMC_A[22](M0) SPI[2]_D[1](M0) HDMI_CEC(M0) TIM4_IO(M2) GP1[17](M0)
0x4814 09BC PINCNTL112 AA26 0x0004 0000 GPMC_A[23](M0) SPI[2]_SCLK(M0) HDMI_HPDET(M0) TIM5_IO(M2) GP1[18](M0)
0x4814 09C0 PINCNTL113 L25 0x0006 0000 SD2_DAT[7] GPMC_A[24](M0) GPMC_A[20](M1) UART2_RXD(M3) GP1[19]
0x4814 09C4 PINCNTL114 N23 0x0006 0000 SD2_DAT[6] GPMC_A[25](M0) GPMC_A[21](M1) UART2_TXD(M3) GP1[20]
0x4814 09C8 PINCNTL115 P22 0x0006 0000 SD2_DAT[5] GPMC_A[26](M0) GPMC_A[22](M1) TIM6_IO(M2) GP1[21]
0x4814 09CC PINCNTL116 R24 0x0006 0000 SD2_DAT[4] GPMC_A[27](M0) GPMC_A[23](M1) GPMC_CS[7] EDMA_EVT0(M1) TIM7_IO(M2) GP1[22]
0x4814 09D0 PINCNTL117 J28 0x0006 0000 SD2_DAT[3] GPMC_A[1](M1) GP2[5](M1)
0x4814 09D4 PINCNTL118 K27 0x0006 0000 SD2_DAT[2]_SDRW GPMC_A[2](M1) GP2[6](M1)
0x4814 09D8 PINCNTL119 M24 0x0006 0000 SD2_DAT[1]_SDIRQ GPMC_A[3](M1) GP1[13](M1)
0x4814 09DC PINCNTL120 L26 0x0006 0000 SD2_DAT[0] GPMC_A[4](M1) GP1[14](M1)
0x4814 09E0 PINCNTL121 M23 0x0006 0000 SD2_CLK GP1[15](M1)
0x4814 09E4 PINCNTL122 T28 0x0006 0000 GPMC_CS[0] GP1[23]
0x4814 09E8 PINCNTL123 K28 0x0006 0000 GPMC_CS[1] GPMC_A[25](M1) GP1[24]
0x4814 09EC PINCNTL124 M25 0x0006 0000 GPMC_CS[2] GPMC_A[24](M1) GP1[25]
0x4814 09F0 PINCNTL125 P26 0x0006 0000 GPMC_CS[3] VIN[1]B_CLK SPI[2]_SCS[0] GP1[26](M0)
0x4814 09F4 PINCNTL126 P25 0x0006 0000 GPMC_CS[4] SD2_CMD GP1[8](M0)
0x4814 09F8 PINCNTL127 R26 0x0006 0000 GPMC_CLK GPMC_CS[5] GPMC_WAIT[1] CLKOUT1 EDMA_EVT3(M0) TIM4_IO(M3) GP1[27]
0x4814 09FC PINCNTL128 M26 0x0006 0000 GPMC_ADV_ALE GPMC_CS[6] TIM5_IO(M3) GP1[28]
0x4814 0A00 PINCNTL129 T27 0x0006 0000 GPMC_OE_RE
0x4814 0A04 PINCNTL130 U28 0x0006 0000 GPMC_WE
0x4814 0A08 PINCNTL131 U27 0x0004 0000 GPMC_BE[0]_CLE GPMC_A[25](M2) EDMA_EVT2(M0) TIM6_IO(M3) GP1[29]
0x4814 0A0C PINCNTL132 V28 0x0004 0000 GPMC_BE[1] GPMC_A[24](M2) EDMA_EVT1(M0) TIM7_IO(M3) GP1[30]
0x4814 0A10 PINCNTL133 W28 0x0006 0000 GPMC_WAIT[0] GPMC_A[26](M2) EDMA_EVT0(M0) GP1[31]
0x4814 0A14 PINCNTL134 AE17 0x0004 0000 VIN[0]B_CLK CLKOUT0 GP1[9](M0)
0x4814 0A18 PINCNTL135 AE21 0x000E 0000 VIN[0]A_DE(M0) VIN[0]B_HSYNC UART5_TXD(M1) I2C[2]_SDA(M1) GP2[0]
0x4814 0A1C PINCNTL136 AA20 0x000E 0000 VIN[0]A_FLD(M0) VIN[0]B_VSYNC UART5_RXD(M1) I2C[2]_SCL(M3) GP2[1]
0x4814 0A20 PINCNTL137 AB20 0x000C 0000 VIN[0]A_CLK GP2[2](M1)
0x4814 0A24 PINCNTL138 AC20 0x000E 0000 VIN[0]A_HSYNC UART5_RTS(M1) GP2[3]
0x4814 0A28 PINCNTL139 AD20 0x000E 0000 VIN[0]A_VSYNC UART5_CTS(M1) GP2[4]
0x4814 0A2C PINCNTL140 AF9 0x000C 0000 VIN[0]A_D[0] GP1[11](M1)
0x4814 0A30 PINCNTL141 AB11 0x000C 0000 VIN[0]A_D[1] GP1[12](M1)
0x4814 0A34 PINCNTL142 AC9 0x000C 0000 VIN[0]A_D[2] GP2[7]
0x4814 0A38 PINCNTL143 AE12 0x000C 0000 VIN[0]A_D[3] GP2[8]
0x4814 0A3C PINCNTL144 AH8 0x000C 0000 VIN[0]A_D[4] GP2[9]
0x4814 0A40 PINCNTL145 AG16 0x000C 0000 VIN[0]A_D[5] GP2[10]
0x4814 0A44 PINCNTL146 AH16 0x000C 0000 VIN[0]A_D[6] GP2[11]
0x4814 0A48 PINCNTL147 AA11 0x000C 0000 VIN[0]A_D[7] GP2[12]
0x4814 0A4C PINCNTL148 AB15 0x000C 0000 VIN[0]A_D[8]_BD[0] GP2[13]
0x4814 0A50 PINCNTL149 AG9 0x000C 0000 VIN[0]A_D[9]_BD[1] GP2[14]
0x4814 0A54 PINCNTL150 AH9 0x000C 0000 VIN[0]A_D[10]_BD[2] GP2[15]
0x4814 0A58 PINCNTL151 AH17 0x000C 0000 VIN[0]A_D[11]_BD[3] CAM_WE(M1) GP2[16]
0x4814 0A5C PINCNTL152 AG17 0x0004 0000 VIN[0]A_D[12]_BD[4] CLKOUT1 GP2[17]
0x4814 0A60 PINCNTL153 AF17 0x000C 0000 VIN[0]A_D[13]_BD[5] CAM_RESET GP2[18]
0x4814 0A64 PINCNTL154 AC12 0x000C 0000 VIN[0]A_D[14]_BD[6] CAM_STROBE GP2[19]
0x4814 0A68 PINCNTL155 AC14 0x000C 0000 VIN[0]A_D[15]_BD[7] CAM_SHUTTER GP2[20]
0x4814 0A6C PINCNTL156 AA21 0x000E 0000 VIN[0]A_D[16] CAM_D[8] I2C[2]_SCL(M1) GP0[10](M0)
0x4814 0A70 PINCNTL157 AB21 0x000C 0000 VIN[0]A_D[17] CAM_D[9] EMAC[1]_RMRXER(M1) GP0[11](M0)
0x4814 0A74 PINCNTL158 AF20 0x000E 0000 VIN[0]A_D[18] CAM_D[10] EMAC[1]_RMRXD[1](M1) I2C[3]_SCL(M2) GP0[12](M0)
0x4814 0A78 PINCNTL159 AF21 0x000E 0000 VIN[0]A_D[19] CAM_D[11] EMAC[1]_RMRXD[0](M1) I2C[3]_SDA(M2) GP0[13](M0)
0x4814 0A7C PINCNTL160 AC17 0x000C 0000 VIN[0]A_D[20] CAM_D[12] EMAC[1]_RMCRSDV(M1) SPI[3]_SCS[0] GP0[14](M0)
0x4814 0A80 PINCNTL161 AE18 0x0004 0000 VIN[0]A_D[21] CAM_D[13] EMAC[1]_RMTXD[0](M1) SPI[3]_SCLK(M0) GP0[15](M0)
0x4814 0A84 PINCNTL162 AC21 0x0004 0000 VIN[0]A_D[22] CAM_D[14] EMAC[1]_RMTXD[1](M1) SPI[3]_D[1](M0) GP0[16](M0)
0x4814 0A88 PINCNTL163 AC16 0x0004 0000 VIN[0]A_D[23] CAM_D[15] EMAC[1]_RMTXEN(M1) SPI[3]_D[0](M0) GP0[17](M0)
0x4814 0A8C PINCNTL164 AB17 0x0006 0000 VIN[0]A_DE(M1) CAM_D[7] GP0[18](M0)
0x4814 0A90 PINCNTL165 AC15 0x0006 0000 VIN[0]B_DE CAM_D[6] GP0[19](M0)
0x4814 0A94 PINCNTL166 AC22 0x0006 0000 VIN[0]A_FLD(M1) CAM_D[5] GP0[20](M0)
0x4814 0A98 PINCNTL167 AD17 0x0006 0000 VIN[0]B_FLD CAM_D[4] GP0[21](M0)
0x4814 0A9C PINCNTL168 AD18 0x0006 0000 VOUT[1]_G_Y_YC[1] CAM_D[3] GPMC_A[5](M1) UART4_RXD(M0) GP0[22](M0)
0x4814 0AA0 PINCNTL169 AC18 0x0004 0000 VOUT[1]_G_Y_YC[0] CAM_D[2] GPMC_A[6](M1) UART4_TXD(M0) GP0[23](M0)
0x4814 0AA4 PINCNTL170 AC19 0x0004 0000 VOUT[1]_R_CR[1] CAM_D[1] GPMC_A[7](M1) UART4_CTS(M0) GP0[24](M0)
0x4814 0AA8 PINCNTL171 AA22 0x0004 0000 VOUT[1]_R_CR[0] CAM_D[0] GPMC_A[8](M1) UART4_RTS(M0) GP0[25](M0)
0x4814 0AAC PINCNTL172 AE23 0x0004 0000 VOUT[1]_B_CB_C[1] CAM_HS GPMC_A[9](M1) UART2_RXD(M0) GP0[26](M0)
0x4814 0AB0 PINCNTL173 AD23 0x0006 0000 VOUT[1]_B_CB_C[0] CAM_VS GPMC_A[10](M1) UART2_TXD(M0) GP0[27](M0)
0x4814 0AB4 PINCNTL174 AB23 0x0004 0000 VOUT[1]_FLD CAM_FLD CAM_WE(M0) GPMC_A[11](M1) UART2_CTS GP0[28](M0)
0x4814 0AB8 PINCNTL175 AF18 0x0004 0000 VOUT[0]_FLD(M1) CAM_PCLK GPMC_A[12](M1) UART2_RTS GP2[2](M0)
0x4814 0ABC PINCNTL176 AD12 0x000C 0000 VOUT[0]_CLK
0x4814 0AC0 PINCNTL177 AC11 0x000C 0000 VOUT[0]_HSYNC
0x4814 0AC4 PINCNTL178 AB13 0x000C 0000 VOUT[0]_VSYNC
0x4814 0AC8 PINCNTL179 AA10 0x000C 0000 VOUT[0]_AVID VOUT[0]_FLD(M0) SPI[3]_SCLK(M2) TIM7_IO(M1) GP2[21]
0x4814 0ACC PINCNTL180 AG7 0x000C 0000
Reset by GCR Only		 VOUT[0]_B_CB_C[2] EMU2 GP2[22]
0x4814 0AD0 PINCNTL181 AE15 0x000C 0000 VOUT[0]_B_CB_C[3] GP2[23]
0x4814 0AD4 PINCNTL182 AD11 0x000C 0000 VOUT[0]_B_CB_C[4]
0x4814 0AD8 PINCNTL183 AD15 0x000C 0000 VOUT[0]_B_CB_C[5]
0x4814 0ADC PINCNTL184 AC10 0x000C 0000 VOUT[0]_B_CB_C[6]
0x4814 0AE0 PINCNTL185 AB10 0x000C 0000 VOUT[0]_B_CB_C[7]
0x4814 0AE4 PINCNTL186 AF15 0x000C 0000 VOUT[0]_B_CB_C[8]
0x4814 0AE8 PINCNTL187 AG15 0x000C 0000 VOUT[0]_B_CB_C[9]
0x4814 0AEC PINCNTL188 AH7 0x000C 0000
Reset by GCR Only		 VOUT[0]_G_Y_YC[2] EMU3 GP2[24]
0x4814 0AF0 PINCNTL189 AH15 0x000C 0000 VOUT[0]_G_Y_YC[3] GP2[25]
0x4814 0AF4 PINCNTL190 AB8 0x000C 0000 VOUT[0]_G_Y_YC[4]
0x4814 0AF8 PINCNTL191 AB12 0x000C 0000 VOUT[0]_G_Y_YC[5]
0x4814 0AFC PINCNTL192 AA8 0x000C 0000 VOUT[0]_G_Y_YC[6]
0x48140B00 PINCNTL193 AD14 0x000C 0000 VOUT[0]_G_Y_YC[7]
0x48140B04 PINCNTL194 AE14 0x000C 0000 VOUT[0]_G_Y_YC[8]
0x48140B08 PINCNTL195 AF14 0x000C 0000 VOUT[0]_G_Y_YC[9]
0x48140B0C PINCNTL196 AD9 0x000C 0000
Reset by GCR Only		 VOUT[0]_R_CR[2] EMU4 GP2[26]
0x4814 0B10 PINCNTL197 AB9 0x000C 0000 VOUT[0]_R_CR[3] GP2[27]
0x4814 0B14 PINCNTL198 AA9 0x000C 0000 VOUT[0]_R_CR[4]
0x4814 0B18 PINCNTL199 AF8 0x000C 0000 VOUT[0]_R_CR[5]
0x4814 0B1C PINCNTL200 AF6 0x000C 0000 VOUT[0]_R_CR[6]
0x4814 0B20 PINCNTL201 AF12 0x000C 0000 VOUT[0]_R_CR[7]
0x4814 0B24 PINCNTL202 AE8 0x000C 0000 VOUT[0]_R_CR[8]
0x4814 0B28 PINCNTL203 AC13 0x000C 0000 VOUT[0]_R_CR[9]
0x4814 0B2C PINCNTL204 AE24 0x0004 0000 VOUT[1]_CLK EMAC[1]_MTCLK VIN[1]A_HSYNC GP2[28]
0x4814 0B30 PINCNTL205 AC24 0x0004 0000 VOUT[1]_HSYNC EMAC[1]_MCOL VIN[1]A_VSYNC SPI[3]_D[1](M2) UART3_RTS(M1) GP2[29]
0x4814 0B34 PINCNTL206 AA23 0x0004 0000 VOUT[1]_VSYNC EMAC[1]_MCRS VIN[1]A_FLD VIN[1]A_DE SPI[3]_D[0](M2) UART3_CTS(M1) GP2[30]
0x4814 0B38 PINCNTL207 Y22 0x0004 0000 VOUT[1]_AVID EMAC[1]_MRXER VIN[1]A_CLK UART4_RTS(M2) TIM6_IO(M1) GP2[31]
0x4814 0B3C PINCNTL208 AH25 0x0004 0000 VOUT[1]_B_CB_C[3] EMAC[1]_MRCLK VIN[1]A_D[0] UART4_CTS(M2) GP3[0]
0x4814 0B40 PINCNTL209 AG25 0x0004 0000 VOUT[1]_B_CB_C[4] EMAC[1]_MRXD[0] VIN[1]A_D[1] UART4_RXD(M2) GP3[1]
0x4814 0B44 PINCNTL210 AF25 0x0004 0000 VOUT[1]_B_CB_C[5] EMAC[1]_MRXD[1] VIN[1]A_D[2] UART4_TXD(M2) GP3[2]
0x4814 0B48 PINCNTL211 AD25 0x0004 0000 VOUT[1]_B_CB_C[6] EMAC[1]_MRXD[2] VIN[1]A_D[3] UART3_RXD(M1) GP3[3]
0x48140B4C PINCNTL212 AC25 0x0004 0000 VOUT[1]_B_CB_C[7] EMAC[1]_MRXD[3] VIN[1]A_D[4] UART3_TXD(M1) GP3[4]
0x4814 0B50 PINCNTL213 AH26 0x0004 0000 VOUT[1]_B_CB_C[8] EMAC[1]_MRXD[4] VIN[1]A_D[5] I2C[3]_SCL(M3) GP3[5]
0x4814 0B54 PINCNTL214 AA24 0x0004 0000 VOUT[1]_B_CB_C[9] EMAC[1]_MRXD[5] VIN[1]A_D[6] I2C[3]_SDA(M3) GP3[6]
0x4814 0B58 PINCNTL215 Y23 0x0004 0000 VOUT[1]_G_Y_YC[3] EMAC[1]_MRXD[6] VIN[1]A_D[8] GP3[7]
0x4814 0B5C PINCNTL216 W22 0x0004 0000 VOUT[1]_G_Y_YC[4] EMAC[1]_MRXD[7] VIN[1]A_D[9] GP3[8]
0x4814 0B60 PINCNTL217 AG26 0x0004 0000 VOUT[1]_G_Y_YC[5] EMAC[1]_MRXDV VIN[1]A_D[10] GP3[9]
0x4814 0B64 PINCNTL218 AH27 0x0004 0000 VOUT[1]_G_Y_YC[6] EMAC[1]_GMTCLK VIN[1]A_D[11] GP3[10]
0x4814 0B68 PINCNTL219 AF26 0x0004 0000 VOUT[1]_G_Y_YC[7] EMAC[1]_MTXD[0] VIN[1]A_D[12] GP3[11]
0x4814 0B6C PINCNTL220 AE26 0x0004 0000 VOUT[1]_G_Y_YC[8] EMAC[1]_MTXD[1] VIN[1]A_D[13] GP3[12]
0x4814 0B70 PINCNTL221 AD26 0x0004 0000 VOUT[1]_G_Y_YC[9] EMAC[1]_MTXD[2] VIN[1]A_D[14] GP3[13]
0x4814 0B74 PINCNTL222 AG27 0x0004 0000 VOUT[1]_R_CR[4] EMAC[1]_MTXD[3] VIN[1]A_D[15] SPI[3]_SCS[1] GP3[14]
0x4814 0B78 PINCNTL223 AC26 0x0004 0000 VOUT[1]_R_CR[5] EMAC[1]_MTXD[4] VIN[1]A_D[16] SPI[3]_SCLK(M1) GP3[15]
0x4814 0B7C PINCNTL224 AA25 0x0004 0000 VOUT[1]_R_CR[6] EMAC[1]_MTXD[5] VIN[1]A_D[17] SPI[3]_D[1](M1) GP3[16]
0x4814 0B80 PINCNTL225 V22 0x0004 0000 VOUT[1]_R_CR[7] EMAC[1]_MTXD[6] VIN[1]A_D[18] SPI[3]_D[0](M1) GP3[17]
0x4814 0B84 PINCNTL226 W23 0x0004 0000 VOUT[1]_R_CR[8] EMAC[1]_MTXD[7] VIN[1]A_D[19] UART5_RXD(M2) GP3[18]
0x4814 0B88 PINCNTL227 Y24 0x0004 0000 VOUT[1]_R_CR[9] EMAC[1]_MTXEN VIN[1]A_D[20] UART5_TXD(M2) GP3[19]
0x4814 0B8C PINCNTL228 AF27 0x0006 0000 VOUT[1]_G_Y_YC[2] GPMC_A[13](M1) VIN[1]A_D[21] HDMI_SCL(M1) SPI[2]_SCS[2] I2C[2]_SCL(M2) GP3[20]
0x4814 0B90 PINCNTL229 AG28 0x0006 0000 VOUT[1]_R_CR[3] GPMC_A[14](M1) VIN[1]A_D[22] HDMI_SDA(M1) SPI[2]_SCLK(M1) I2C[2]_SDA(M2) GP3[21]
0x4814 0B94 PINCNTL230 AE27 0x0004 0000 VOUT[1]_R_CR[2] GPMC_A[15](M1) VIN[1]A_D[23] HDMI_HPDET(M1) SPI[2]_D[1](M1) GP3[22]
0x4814 0B98 PINCNTL231 AF28 0x0006 0000 VOUT[1]_B_CB_C[2] GPMC_A[0](M1) VIN[1]A_D[7] HDMI_CEC(M1) SPI[2]_D[0](M1) GP3[30](M1)
0x4814 0B9C PINCNTL232 J27 0x0004 0000 EMAC_RMREFCLK TIM2_IO(M3) GP1[10](M0)
0x4814 0BA0 PINCNTL233 H28 0x000E 0000 MDCLK GP1[11](M0)
0x4814 0BA4 PINCNTL234 P24 0x000E 0000 MDIO GP1[12](M0)
0x4814 0BA8 PINCNTL235 L24 0x000C 0000 EMAC[0]_MTCLK/
EMAC[0]_RGRXC		 VIN[1]B_D[0] SPI[3]_SCS[3] I2C[2]_SDA(M3) GP3[23]
0x4814 0BAC PINCNTL236 L23 0x000C 0000 EMAC[0]_MCOL/
EMAC[0]_RGRXCTL		 VIN[1]B_D[1] EMAC[0]_RMRXD[0] GP3[24]
0x4814 0BB0 PINCNTL237 R25 0x000C 0000 EMAC[0]_MCRS/
EMAC[0]_RGRXD[2]		 VIN[1]B_D[2] EMAC[0]_RMRXD[1] GP3[25]
0x4814 0BB4 PINCNTL238 J26 0x000C 0000 EMAC[0]_MRXER/
EMAC[0]_RGTXCTL		 VIN[1]B_D[3] EMAC[0]_RMRXER GP3[26]
0x4814 0BB8 PINCNTL239 H27 0x000C 0000 EMAC[0]_MRCLK/
EMAC[0]_RGTXC		 VIN[1]B_D[4] EMAC[0]_RMCRSDV SPI[3]_SCS[2] GP3[27]
0x4814 0BBC PINCNTL240 G28 0x0004 0000 EMAC[0]_MRXD[0]/
EMAC[0]_RGTXD[0]		 VIN[1]B_D[5] EMAC[0]_RMTXD[0] GP3[28]
0x4814 0BC0 PINCNTL241 P23 0x0004 0000 EMAC[0]_MRXD[1]/
EMAC[0]_RGRXD[0]		 VIN[1]B_D[6] EMAC[0]_RMTXD[1] GP3[29]
0x4814 0BC4 PINCNTL242 R23 0x0004 0000 EMAC[0]_MRXD[2]/
EMAC[0]_RGRXD[1]		 VIN[1]B_D[7] EMAC[0]_RMTXEN GP3[30](M0)
0x4814 0BC8 PINCNTL243 J25 0x0004 0000 EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL		 GPMC_A[27](M1) GPMC_A[26](M1) GPMC_A[0](M0) UART5_RXD(M0)
0x4814 0BCC PINCNTL244 T23 0x0004 0000 EMAC[0]_MRXD[4]/
EMAC[0]_RGRXD[3]		 GPMC_A[1](M0) UART5_TXD(M0)
0x4814 0BD0 PINCNTL245 H26 0x0004 0000 EMAC[0]_MRXD[5]/
EMAC[0]_RGTXD[3]		 GPMC_A[2](M0) UART5_CTS(M0)
0x4814 0BD4 PINCNTL246 F28 0x0004 0000 EMAC[0]_MRXD[6]/
EMAC[0]_RGTXD[2]		 GPMC_A[3](M0) UART5_RTS(M0)
0x4814 0BD8 PINCNTL247 G27 0x0004 0000 EMAC[0]_MRXD[7]/
EMAC[0]_RGTXD[1]		 GPMC_A[4](M0) SPI[2]_SCS[3]
0x4814 0BDC PINCNTL248 K22 0x0004 0000 EMAC[0]_MRXDV/
EMAC[1]_RGRXD[1]		 GPMC_A[5](M0) SPI[2]_SCLK(M2)
0x4814 0BE0 PINCNTL249 K23 0x0004 0000 EMAC[0]_GMTCLK/
EMAC[1]_RGRXC		 GPMC_A[6](M0) SPI[2]_D[1](M2)
0x4814 0BE4 PINCNTL250 J24 0x0004 0000 EMAC[0]_MTXD[0]/
EMAC[1]_RGRXD[3]		 GPMC_A[7](M0) SPI[2]_D[0](M2)
0x4814 0BE8 PINCNTL251 H25 0x0004 0000 EMAC[0]_MTXD[1]/
EMAC[1]_RGTXD[1]		 GPMC_A[8](M0) UART4_RXD(M1)
0x4814 0BEC PINCNTL252 H22 0x0004 0000 EMAC[0]_MTXD[2]/
EMAC[1]_RGTXCTL		 EMAC[1]_RMRXD[0](M0) GPMC_A[9](M0) UART4_TXD(M1)
0x4814 0BF0 PINCNTL253 H23 0x0004 0000 EMAC[0]_MTXD[3]/
EMAC[1]_RGTXD[0]		 EMAC[1]_RMRXD[1](M0) GPMC_A[10](M0) UART4_CTS(M1)
0x4814 0BF4 PINCNTL254 G23 0x0004 0000 EMAC[0]_MTXD[4]/
EMAC[1]_RGTXD[2]		 EMAC[1]_RMRXER GPMC_A[11](M0) UART4_RTS(M1)
0x4814 0BF8 PINCNTL255 F27 0x0004 0000 EMAC[0]_MTXD[5]/
EMAC[1]_RGTXC		 EMAC[1]_RMCRSDV(M0) GPMC_A[12](M0) UART1_RXD(M1)
0x4814 0BFC PINCNTL256 J22 0x0004 0000 EMAC[0]_MTXD[6]/
EMAC[1]_RGRXD[0]		 EMAC[1]_RMTXD[0](M0) GPMC_A[13](M0) UART1_TXD(M1)
0x4814 0C00 PINCNTL257 H24 0x0004 0000 EMAC[0]_MTXD[7]/
EMAC[1]_RGTXD[3]		 EMAC[1]_RMTXD[1](M0) GPMC_A[14](M0) UART1_CTS
0x4814 0C04 PINCNTL258 J23 0x0004 0000 EMAC[0]_MTXEN/
EMAC[1]_RGRXD[2]		 EMAC[1]_RMTXEN(M0) GPMC_A[15](M0) UART1_RTS
0x4814 0C08 PINCNTL259 J7 0x0004 0000 CLKIN32 CLKOUT0 TIM3_IO(M3) GP3[31]
0x4814 0C0C PINCNTL260 J5 0x000E 0000 RESET
0x4814 0C10 PINCNTL261 H7 0x000E 0000 NMI
0x4814 0C14 PINCNTL262 K6 0x0005 0000 RSTOUT_WD_OUT
0x4814 0C18 PINCNTL263 AC4 0x000D 0000 I2C[0]_SCL
0x4814 0C1C PINCNTL264 AB6 0x000D 0000 I2C[0]_SDA
0x4814 0C20 PINCNTL265 – Undetermined Reserved. Do Not Program this Register.
0x4814 0C24 PINCNTL266 – Undetermined Reserved. Do Not Program this Register.
0x4814 0C28 PINCNTL267 – Undetermined Reserved. Do Not Program this Register.
0x4814 0C2C PINCNTL268 – Undetermined Reserved. Do Not Program this Register.
0x4814 0C30 PINCNTL269 – Undetermined Reserved. Do Not Program this Register.
0x4814 0C34 PINCNTL270 AF11 0x000C 0000 USB0_DRVVBUS GP0[7]

3.4 Handling Unused Pins

When device signal pins are unused in the system, they can be left unconnected unless otherwise noted in the Terminal Functions tables (see Section 2.11). For unused input pins, the internal pull resistor should be enabled, or an external pull resistor should be used, to prevent floating inputs. Unless otherwise noted, all supply pins must always be connected to the correct voltage, even when their associated signal pins are unused.

3.5 DeBugging Considerations

3.5.1 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the AM387x Sitara™ ARM Processors device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.

An external pullup/pulldown resistor must be used in the following situations:

  • Boot Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state.
  • Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail.

For the boot configuration pins (listed in Table 2-1, Boot Configuration Terminal Functions), if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device boot configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

  • Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors.
  • Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which, by definition, have margin to the VIL and VIH levels.
  • Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net.
  • For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin).
  • Remember to include tolerances when selecting the resistor value.
  • For pullup resistors, also remember to include tolerances on the DVDD rail.

For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For most systems, a 20-kΩ resistor can also be used as an external PU/PD on the pins that have IPUs/IPDs disabled and require an external PU/PD resistor while still meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH) for the device, see Section 5.4, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature.

For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functions table.