2 Revision History
Changes from July 16, 2018 to May 15, 2019 (from D Revision (July 2018) to E Revision)
- Added clarification notes for EMU[1:0] connections to Table 4-21, GPIOs Signal Descriptions and Table 4-25, Debug Signal DescriptionsGo
- Updated Table 5-3, AVS and ABB Requirements per vdd_* SupplyGo
- Updated OPP_HIGH voltage range in note (6) under Table 5-4, Voltage Domains Operating Performance PointsGo
- Added Ivpp specification in Table 5-15, Recommended Operating Conditions for OTP eFuse ProgrammingGo
- Updated notes regarding porz and rstoutn timing under Figure 5-5, Power-Up SequencingGo
- Updated EMIF_DLL_FCLK max rate in Table 5-29, DLL CharacteristicsGo
- Added MII_TXER timing to Section 5.10.6.19.1, GMAC MII TimingsGo
- Updated Figure 5-68, GMAC MDIO diagrams and MDIO7 parameter values in Table 5-97, Switching Characteristics Over Recommended Operating Conditions for MDIO OutputGo
- Added note regarding DDR ECC solutions to Table 7-4, Supported DDR3 Device CombinationsGo
- Added clarifications about validated DDR topology in Section 7.2.2.15, CK and ADDR_CTRL Topologies and Routing DefinitionGo