SPRSP08H November   2017  – June 2019 AM6526 , AM6527 , AM6528 , AM6546 , AM6548

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  ADC
        1. 4.3.1.1 MCU Domain
      2. 4.3.2  CAL
        1. 4.3.2.1 MAIN Domain
      3. 4.3.3  CPSW2G
        1. 4.3.3.1 MCU Domain
      4. 4.3.4  DDRSS
        1. 4.3.4.1 MAIN Domain
        2. 4.3.4.2 DDRSS Mapping
      5. 4.3.5  DMTIMER
        1. 4.3.5.1 MAIN Domain
        2. 4.3.5.2 MCU Domain
      6. 4.3.6  DSS
        1. 4.3.6.1 MAIN Domain
      7. 4.3.7  ECAP
        1. 4.3.7.1 MAIN Domain
      8. 4.3.8  EHRPWM
        1. 4.3.8.1 MAIN Domain
      9. 4.3.9  EQEP
        1. 4.3.9.1 MAIN Domain
      10. 4.3.10 GPIO
        1. 4.3.10.1 MAIN Domain
        2. 4.3.10.2 WKUP Domain
      11. 4.3.11 GPMC
        1. 4.3.11.1 MAIN Domain
      12. 4.3.12 HYPERBUS
        1. 4.3.12.1 MCU Domain
      13. 4.3.13 I2C
        1. 4.3.13.1 MAIN Domain
        2. 4.3.13.2 MCU Domain
        3. 4.3.13.3 WKUP Domain
      14. 4.3.14 MCAN
        1. 4.3.14.1 MCU Domain
      15. 4.3.15 MCASP
        1. 4.3.15.1 MAIN Domain
      16. 4.3.16 MCSPI
        1. 4.3.16.1 MAIN Domain
        2. 4.3.16.2 MCU Domain
      17. 4.3.17 MMC
        1. 4.3.17.1 MAIN Domain
      18. 4.3.18 CPTS
        1. 4.3.18.1 MAIN Domain
      19. 4.3.19 OLDI
        1. 4.3.19.1 MAIN Domain
      20. 4.3.20 OSPI
        1. 4.3.20.1 MCU Domain
      21. 4.3.21 PRU_ICSSG
        1. 4.3.21.1 MAIN Domain
      22. 4.3.22 SERDES
        1. 4.3.22.1 MAIN Domain
      23. 4.3.23 UART
        1. 4.3.23.1 MAIN Domain
        2. 4.3.23.2 MCU Domain
        3. 4.3.23.3 WKUP Domain
      24. 4.3.24 USB
        1. 4.3.24.1 MAIN Domain
      25. 4.3.25 Emulation and Debug
        1. 4.3.25.1 MAIN Domain
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Boot Mode Configuration
          1. 4.3.26.1.1 MAIN Domain
          2. 4.3.26.1.2 MCU Domain
        2. 4.3.26.2 Clock
          1. 4.3.26.2.1 MAIN Domain
          2. 4.3.26.2.2 WKUP Domain
        3. 4.3.26.3 System
          1. 4.3.26.3.1 MAIN Domain
          2. 4.3.26.3.2 WKUP Domain
        4. 4.3.26.4 Miscellaneous
          1. 4.3.26.4.1 WKUP Domain
        5. 4.3.26.5 EFUSE
          1. 4.3.26.5.1 MAIN Domain
          2. 4.3.26.5.2 MCU Domain
      27. 4.3.27 Power Supply
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On-Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 Core Clock Specifications
    6. 5.6 Electrical Characteristics
      1. Table 5-3  I2C OPEN DRAIN DC Electrical Characteristics
      2. Table 5-4  Analog OSC Buffers DC Electrical Characteristics
      3. Table 5-5  UHS-I MMC (8-bit PHY) Buffers DC Electrical Characteristics
      4. Table 5-6  Analog ADC DC Electrical Characteristics
      5. Table 5-7  DPHY CSI2 Buffers DC Electrical Characteristics
      6. Table 5-8  OLDI LVDS Buffers DC Electrical Characteristics
      7. Table 5-9  LVCMOS Buffers DC Electrical Characteristics
      8. Table 5-10 LVCMOS-FS Buffers DC Electrical Characteristics
      9. 5.6.1      USBHS Buffers DC Electrical Characteristics
      10. 5.6.2      SERDES Buffers DC Electrical Characteristics
    7. 5.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-11 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.7.1      Hardware Requirements
      3. 5.7.2      Programming Sequence
      4. 5.7.3      Impact to Your Hardware Warranty
    8. 5.8 Thermal Resistance Characteristics
      1. Table 5-12 Thermal Resistance Characteristics
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Timing Parameters and Information
      2. 5.9.2 Power Supply Sequencing
        1. 5.9.2.1 Power Supply Slew Rate Requirement
        2. 5.9.2.2 Power-Up Sequencing
        3. 5.9.2.3 Power-Down Sequencing
      3. 5.9.3 Reset Timing
        1. 5.9.3.1 Reset Electrical Data/Timing
      4. 5.9.4 Clock Specifications
        1. 5.9.4.1 Input Clocks / Oscillators
          1. 5.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
          2. 5.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 5.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
          4. 5.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 5.9.4.1.5 Auxiliary OSC1 Not Used
          6. 5.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 5.9.4.1.7 WKUP_LFOSC0 Not Used
        2. 5.9.4.2 Output Clocks
        3. 5.9.4.3 PLLs
        4. 5.9.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 5.9.4.5 Interface Clock Specifications
          1. 5.9.4.5.1 Interface Clock Terminology
          2. 5.9.4.5.2 Interface Clock Frequency
      5. 5.9.5 Peripherals
        1. 5.9.5.1  VIN
        2. 5.9.5.2  CPSW2G
          1. 5.9.5.2.1 CPSW2G MDIO Interface Timings
          2. 5.9.5.2.2 CPSW2G RMII Timings
            1. Table 5-30 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. Table 5-31 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. Table 5-32 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          3. 5.9.5.2.3 CPSW2G RGMII Timings
            1. Table 5-33 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. Table 5-34 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. Table 5-35 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. Table 5-36 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
        3. 5.9.5.3  CSI2
        4. 5.9.5.4  DDRSS
        5. 5.9.5.5  DSS
        6. 5.9.5.6  eCAP
          1. Table 5-40 Timing Requirements for eCAP
          2. Table 5-41 Switching Characteristics for eCAP
        7. 5.9.5.7  eHRPWM
          1. Table 5-42 Timing Requirements for eHRPWM
          2. Table 5-43 Switching Characteristics for eHRPWM
        8. 5.9.5.8  eQEP
          1. Table 5-44 Timing Requirements for eQEP
          2. Table 5-45 Switching Characteristics for eQEP
        9. 5.9.5.9  GPIO
          1. Table 5-46 GPIO Timing Requirements
          2. Table 5-47 GPIO Switching Characteristics
        10. 5.9.5.10 GPMC
          1. 5.9.5.10.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-48 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            2. Table 5-49 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.9.5.10.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-50 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            2. Table 5-51 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 5.9.5.10.3 GPMC and NAND Flash—Asynchronous Mode
            1. Table 5-52 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            2. Table 5-53 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        11. 5.9.5.11 HYPERBUS
          1. Table 5-54 Timing Requirements for HyperBus Initialization
          2. Table 5-55 HyperBus 166 MHz Switching Characteristics
          3. Table 5-56 HyperBus 100 MHz Switching Characteristics
        12. 5.9.5.12 I2C
          1. Table 5-57 Timing Requirements for I2C Input Timings
          2. Table 5-58 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        13. 5.9.5.13 MCAN
        14. 5.9.5.14 MCASP
          1. Table 5-60 Timing Requirements for MCASP
        15. 5.9.5.15 MCSPI
          1. 5.9.5.15.1 SPI—Master Mode
            1. Table 5-62 Timing Requirements for SPI - Master Mode
          2. 5.9.5.15.2 MCSPI—Slave Mode
            1. Table 5-63 Timing Requirements for SPI - Slave Mode
        16. 5.9.5.16 eMMC/SD/SDIO
          1. 5.9.5.16.1 MMCi — eMMC/SD/SDIO Card Interface
            1. 5.9.5.16.1.1 Default speed Mode
            2. 5.9.5.16.1.2 High speed Mode
            3. 5.9.5.16.1.3 UHS-I SDR12 Mode
            4. 5.9.5.16.1.4 UHS-I SDR25 Mode
            5. 5.9.5.16.1.5 UHS-I SDR50 Mode
            6. 5.9.5.16.1.6 UHS-I SDR104 / HS200 Mode
            7. 5.9.5.16.1.7 UHS-I DDR50 Mode
        17. 5.9.5.17 NAVSS
          1. Table 5-77 Timing Requirements for CPTS Input
          2. Table 5-78 Switching Characteristics for CPTS Output
        18. 5.9.5.18 OSPI
          1. 5.9.5.18.1 OSPI with Data Training
            1. Table 5-79 OSPI Switching Characteristics - Data Training
          2. 5.9.5.18.2 OSPI without Data Training
            1. Table 5-80 OSPI Switching Characteristics - DDR Mode
            2. Table 5-81 OSPI Switching Characteristics - SDR Mode
            3. Table 5-82 OSPI Timing Requirements - DDR Mode
            4. Table 5-83 OSPI Timing Requirements - SDR Mode
        19. 5.9.5.19 OLDI
          1. Table 5-85 OLDI Switching Characteristics
        20. 5.9.5.20 PCIE
        21. 5.9.5.21 PRU_ICSSG
          1. 5.9.5.21.1 Programmable Real-Time Unit (PRU_ICSSG PRU)
            1. 5.9.5.21.1.1 PRU_ICSSG PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-86 PRU_ICSSG PRU Timing Requirements - Direct Input Mode
              2. Table 5-87 PRU_ICSSG PRU Switching Characteristics - Direct Output Mode
            2. 5.9.5.21.1.2 PRU_ICSSG PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-88 PRU_ICSSG PRU Timing Requirements - Parallel Capture Mode
            3. 5.9.5.21.1.3 PRU_ICSSG PRU Shift Mode Electrical Data and Timing
              1. Table 5-89 PRU_ICSSG PRU Timing Requirements - Shift In Mode
              2. Table 5-90 PRU_ICSSG PRU Switching Characteristics - Shift Out Mode
            4. 5.9.5.21.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Modes Electrical Data and Timing
              1. Table 5-91 PRU_ICSSG PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-92 PRU_ICSSG PRU Timing Requirements - Peripheral Interface Mode
              3. Table 5-93 PRU_ICSSG PRU Switching Characteristics - Peripheral Interface Mode
          2. 5.9.5.21.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 5.9.5.21.2.1 PRU_ICSSG PWM Electrical Data and Timing
              1. Table 5-94 PRU_ICSSG PWM Switching Characteristics
          3. 5.9.5.21.3 PRU_ICSSG Industrial Ethernet Peripheral (PRU_ICSSG IEP)
            1. 5.9.5.21.3.1 PRU_ICSSG IEP Electrical Data and Timing
              1. Table 5-95 PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx
              2. Table 5-96 PRU_ICSSG IEP Timing Requirements - Digital IOs
              3. Table 5-97 PRU_ICSSG IEP Timing Requirements - LATCHx_IN
          4. 5.9.5.21.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. 5.9.5.21.4.1 PRU_ICSSG UART Electrical Data and Timing
              1. Table 5-98 PRU_ICSSG UART Timing Requirements
              2. Table 5-99 PRU_ICSSG UART Switching Characteristics
          5. 5.9.5.21.5 PRU_ICSSG Enhanced Capture Peripheral (PRU-ICSS ECAP)
            1. 5.9.5.21.5.1 PRU_ICSSG ECAP Electrical Data and Timing
              1. Table 5-100 PRU_ICSSG ECAP Timing Requirements
              2. Table 5-101 PRU_ICSSG ECAP Switching Characteristics
          6. 5.9.5.21.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 5.9.5.21.6.1 PRU_ICSSG MDIO Electrical Data and Timing
              1. Table 5-102 PRU_ICSSG MDIO Timing Requirements – MDIO_DATA
              2. Table 5-103 PRU_ICSSG MDIO Switching Characteristics – MDIO_CLK
              3. Table 5-104 PRU_ICSSG MDIO Switching Characteristics – MDIO_DATA
            2. 5.9.5.21.6.2 PRU_ICSSG RGMII Electrical Data and Timing
              1. Table 5-105 PRU_ICSSG RGMII Timing Requirements - RGMII_RCLK
              2. Table 5-106 PRU_ICSSG RGMII Timing Requirements - RGMII_RD[3:0] and RGMII_RCTL
              3. Table 5-107 PRU_ICSSG RGMII Switching Characteristics - RGMII_TCLK
              4. Table 5-108 PRU_ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TCTL
            3. 5.9.5.21.6.3 PRU_ICSSG MII_RT Electrical Data and Timing
              1. Table 5-109 PRU_ICSSG MII_RT Timing Requirements – MII_RXCLK
              2. Table 5-110 PRU_ICSSG MII_RT Timing Requirements – MII_TXCLK
              3. Table 5-111 PRU_ICSSG MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-112 PRU_ICSSG MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
        22. 5.9.5.22 Timers
          1. Table 5-113 Timing Requirements for Timers
          2. Table 5-114 Switching Characteristics for Timers
        23. 5.9.5.23 UART
          1. Table 5-115 Timing Requirements for UART
          2. Table 5-116 Switching Characteristics Over Recommended Operating Conditions for UART
        24. 5.9.5.24 USB
      6. 5.9.6 Emulation and Debug
        1. 5.9.6.1 Debug Trace
        2. 5.9.6.2 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.9.6.2.1 JTAG Electrical Data and Timing
            1. Table 5-118 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-119 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Processor Subsystems
      1. 6.2.1 Arm Cortex-A53
      2. 6.2.2 Arm Cortex-R5F
    3. 6.3 Accelerators and Coprocessors
      1. 6.3.1 PRU_ICSSG
      2. 6.3.2 GPU
    4. 6.4 Other Subsystems
      1. 6.4.1 DMSC
      2. 6.4.2 MSMC
      3. 6.4.3 NAVSS
        1. 6.4.3.1 NAVSS0
        2. 6.4.3.2 MCU_NAVSS
      4. 6.4.4 PDMA Controller
        1. 6.4.4.1 PDMA Features
          1. 6.4.4.1.1 MCU_PDMA0 Features
          2. 6.4.4.1.2 MCU_PDMA1 Features
          3. 6.4.4.1.3 PDMA0 Features
          4. 6.4.4.1.4 PDMA1 Features
          5. 6.4.4.1.5 PDMA_DEBUG Features
      5. 6.4.5 Peripherals
        1. 6.4.5.1  ADC
        2. 6.4.5.2  CAL
        3. 6.4.5.3  CPSW2G
        4. 6.4.5.4  DCC
        5. 6.4.5.5  DDRSS
        6. 6.4.5.6  DSS
        7. 6.4.5.7  ЕCAP
        8. 6.4.5.8  EPWM
        9. 6.4.5.9  ELM
        10. 6.4.5.10 ESM
        11. 6.4.5.11 EQEP
        12. 6.4.5.12 GPIO
        13. 6.4.5.13 GPMC
        14. 6.4.5.14 HYPERBUS
        15. 6.4.5.15 I2C
        16. 6.4.5.16 MCAN
        17. 6.4.5.17 MCASP
        18. 6.4.5.18 MCRC
        19. 6.4.5.19 MCSPI
        20. 6.4.5.20 MMC/SD
        21. 6.4.5.21 OSPI
        22. 6.4.5.22 PCIE
        23. 6.4.5.23 SerDes
        24. 6.4.5.24 RTI
        25. 6.4.5.25 Timers
        26. 6.4.5.26 UART
        27. 6.4.5.27 USB
    5. 6.5 Identification
      1. 6.5.1 Revision Identification
      2. 6.5.2 Die Identification
      3. 6.5.3 JTAG Identification
      4. 6.5.4 ROM Code Identification
    6. 6.6 Boot Modes
      1. 6.6.1 Boot Mode List
      2. 6.6.2 Boot Mode Pin Usage
        1. 6.6.2.1 MCU_BOOTMODE Pin Mapping
        2. 6.6.2.2 BOOTMODE Pin Mapping
          1. 6.6.2.2.1 Primary Boot Mode Configuration
          2. 6.6.2.2.2 Backup Boot Mode Configuration
      3. 6.6.3 Boot Mode Selection
        1. 6.6.3.1 Primary Boot Mode Selection
        2. 6.6.3.2 Backup Boot Mode Selection
        3. 6.6.3.3 Min Pin
  7. 7Applications, Implementation, and Layout
    1. 7.1 DDR Board Design and Layout Guidelines
    2. 7.2 OSPI Board Design and Layout Guidelines
      1. 7.2.1 No Loopback & Internal Pad Loopback
      2. 7.2.2 External Board Loopback
      3. 7.2.3 DQS (only available in Octal Flash devices)
    3. 7.3 High Speed Differential Signal Routing Guidance
    4. 7.4 USB Design Guidelines
    5. 7.5 System Power Supply Monitor Design Guidelines
    6. 7.6 MMC Design Guidelines
    7. 7.7 Power Distribution Network Implementation Guidance
    8. 7.8 External Capacitors
      1. 7.8.1 LVCMOS External Capacitor Connections
    9. 7.9 Thermal Solution Guidance
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Overview