SWRS188B May   2017  – September 2019 AWR1243

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Supply Specifications
    6. 5.6 Power Consumption Summary
    7. 5.7 RF Specification
    8. 5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Power Supply Sequencing and Reset Timing
      2. 5.9.2 Synchronized Frame Triggering
      3. 5.9.3 Input Clocks and Oscillators
        1. 5.9.3.1 Clock Specifications
      4. 5.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.9.4.1 Peripheral Description
          1. Table 5-8  SPI Timing Conditions
          2. Table 5-9  SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. Table 5-10 SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 5.9.4.2 Typical Interface Protocol Diagram (Slave Mode)
      5. 5.9.5 LVDS Interface Configuration
        1. 5.9.5.1 LVDS Interface Timings
      6. 5.9.6 General-Purpose Input/Output
        1. Table 5-12 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 5.9.7 Camera Serial Interface (CSI)
        1. Table 5-13 CSI Switching Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Host Interface
    4. 6.4 Other Subsystems
      1. 6.4.1 A2D Data Format Over CSI2 Interface
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Short-, Medium-, and Long-Range Radar
    3. 7.3 Imaging Radar using Cascade Configuration
    4. 7.4 Reference Schematic
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Stackup Details
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

LVDS Interface Configuration

The AWR1243 supports seven differential LVDS IOs/Lanes to support debug where raw ADC data could be extracted. The lane configuration supported is four Data lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface supports the following data rates:

  • 900 Mbps (450 MHz DDR Clock)
  • 600 Mbps (300 MHz DDR Clock)
  • 450 Mbps (225 MHz DDR Clock)
  • 400 Mbps (200 MHz DDR Clock)
  • 300 Mbps (150 MHz DDR Clock)
  • 225 Mbps (112.5 MHz DDR Clock)
  • 150 Mbps (75 MHz DDR Clock)

Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.

AWR1243 lvds_interface_lane_config.gifFigure 5-7 LVDS Interface Lane Configuration And Relative Timings