SWRS188B May   2017  – September 2019 AWR1243

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Supply Specifications
    6. 5.6 Power Consumption Summary
    7. 5.7 RF Specification
    8. 5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Power Supply Sequencing and Reset Timing
      2. 5.9.2 Synchronized Frame Triggering
      3. 5.9.3 Input Clocks and Oscillators
        1. 5.9.3.1 Clock Specifications
      4. 5.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.9.4.1 Peripheral Description
          1. Table 5-8  SPI Timing Conditions
          2. Table 5-9  SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. Table 5-10 SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 5.9.4.2 Typical Interface Protocol Diagram (Slave Mode)
      5. 5.9.5 LVDS Interface Configuration
        1. 5.9.5.1 LVDS Interface Timings
      6. 5.9.6 General-Purpose Input/Output
        1. Table 5-12 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 5.9.7 Camera Serial Interface (CSI)
        1. Table 5-13 CSI Switching Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Host Interface
    4. 6.4 Other Subsystems
      1. 6.4.1 A2D Data Format Over CSI2 Interface
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Short-, Medium-, and Long-Range Radar
    3. 7.3 Imaging Radar using Cascade Configuration
    4. 7.4 Reference Schematic
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Stackup Details
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Signal Descriptions

Table 4-1 lists the pins by function and describes that function.

NOTE

All IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply being present to the device.

Table 4-1 Signal Descriptions

FUNCTION SIGNAL NAME PIN NUMBER PIN TYPE DEFAULT PULL STATUS(1) DESCRIPTION
Transmitters TX1 B4 O Single-ended transmitter1 o/p
TX2 B6 O Single-ended transmitter2 o/p
TX3 B8 O Single-ended transmitter3 o/p
Receivers RX1 M2 I Single-ended receiver1 i/p
RX2 K2 I Single-ended receiver2 i/p
RX3 H2 I Single-ended receiver3 i/p
RX4 F2 I Single-ended receiver4 i/p
CSI2 TX CSI2_TXP[0] G15 O Differential data Out – Lane 0 (for CSI and LVDS debug interface)
CSI2_TXM[0] G14 O
CSI2_CLKP J15 O Differential clock Out (for CSI and LVDS debug interface)
CSI2_CLKM J14 O
CSI2_TXP[1] H15 O Differential data Out – Lane 1 (for CSI and LVDS debug interface)
CSI2_TXM[1] H14 O
CSI2_TXP[2] K15 O Differential data Out – Lane 2 (for CSI and LVDS debug interface)
CSI2_TXM[2] K14 O
CSI2_TXP[3] L15 O Differential data Out – Lane 3 (for CSI and LVDS debug interface)
CSI2_TXM[3] L14 O
HS_DEBUG1_P M15 O Differential debug port 1 (for LVDS debug interface)
HS_DEBUG1_M M14 O
HS_DEBUG2_P N15 O Differential debug port 2 (for LVDS debug interface)
HS_DEBUG2_M N14 O
Chip-to-chip cascading synchronization signals(2) FM_CW_CLKOUT B15 O 20-GHz single-ended output. Modulated waveform
FM_CW_SYNCOUT D1
FM_CW_SYNCIN1 B1 I 20-GHz single-ended input. Only one of these pins should be used. Multiple instances for layout flexibility.
FM_CW_SYNCIN2 D15
Reference clock OSC_CLKOUT A14 O Reference clock output from clocking subsystem after cleanup PLL. Can be used by slave chip in multichip cascading
System synchronization SYNC_OUT P11 O Pull Down Low-frequency frame synchronization signal output. Can be used by slave chip in multichip cascading
SYNC_IN N10 I Pull Down Low-frequency frame synchronization signal input.
This signal could also be used as a hardware trigger for frame start
SPI control interface from external MCU (default slave mode) SPI_CS_1 R7 I Pull Up SPI chip select
SPI_CLK_1 R9 I Pull Down SPI clock
MOSI_1 R8 I Pull Up SPI data input
MISO_1 P5 O Pull Up SPI data output
SPI_HOST_INTR_1 P6 O Pull Down SPI interrupt to host
RESERVED R3, R4, R5, P4
Reset NRESET P12 I Open Drain Power on reset for chip. Active low
WARM_RESET(3) N12 IO Open Drain Open-drain fail-safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset.
SOP2 P13 I The SOP pins are driven externally (weak drive) and the AWR device senses the state of these pins during bootup to decide the bootup mode. After boot the same pins have other functionality.
[SOP2 SOP1 SOP0] = [0 0 1] → Functional SPI mode
[SOP2 SOP1 SOP0] = [1 0 1] → Flashing mode
[SOP2 SOP1 SOP0] = [0 1 1] → debug mode
Sense on Power SOP1 P11 I
SOP0 J13 I
Safety NERROR_OUT N8 O Open Drain Open-drain fail-safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset.
NERROR_IN P7 I Open Drain Fail-safe input to the device. Error output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by firmware
JTAG TMS L13 I Pull Up JTAG port for TI internal development
TCK M13 I Pull Down
TDI H13 I Pull Up
TDO J13 O
Reference oscillator CLKP E14 I In XTAL mode: Differential port for reference crystal
In External clock mode: Single ended input reference clock port (Output CLKM is grounded in this case)
CLKM F14 O
Band-gap voltage VBGAP B10 O
Power supply VDDIN F13,N11,P15,R6 POW 1.2-V digital power supply
VIN_SRAM R14 POW 1.2-V power rail for internal SRAM
VNWA P14 POW 1.2-V power rail for SRAM array back bias
VIOIN R13 POW I/O supply (3.3-V or 1.8-V): All CMOS I/Os would operate on this supply.
VIOIN_18 K13 POW 1.8-V supply for CMOS IO
VIN_18CLK B11 POW 1.8-V supply for clock module
VIOIN_18DIFF D13 POW 1.8-V supply for CSI2 port
Reserved G13 POW No connect
VIN_13RF1 G5,J5,H5 POW 1.3-V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the board
VIN_13RF2 C2,D2 POW
VIN_18BB K5,F5 POW 1.8-V Analog baseband power supply
VIN_18VCO B12 POW 1.8-V RF VCO supply
VSS E5,E6,E8,E10,E11,F9,F11,G6,G7,G8,G10,H7,H9,H11,J6,J7,J8,J10,K7,K8,K9,K10,K11,L5,L6,L8,L10,R15 GND Digital ground
VSSA A1,A3,A5,A7,A9,A15,B3,B5,B7,B9,B13,B14,C1,C3,C4,C5,C6,C7,C8,C9,C15,E1,E2,E3,E13,E15,F3,G1,G2,G3,H3,J1,J2,J3,K3,L1,L2,L3, M3,N1,N2,N3,R1 GND Analog ground
Internal LDO output/inputs VOUT_14APLL A10 O
VOUT_14SYNTH A13 O
VOUT_PA A2,B2 IO When internal PA LDO is used this pin provides the output voltage of the LDO. When the internal PA LDO is bypassed and disabled 1V supply should be fed on this pin. This is mandatory in 3TX simultaneous use case.
External clock out PMIC_CLK_OUT P13 O Dithered clock input to PMIC
MCU_CLK_OUT N9 O Programmable clock given out to external MCU or the processor
General-purpose I/Os GPIO[0] N4 IO Pull Down General-purpose IO
GPIO[1] N7 IO Pull Down General-purpose IO
GPIO[2] N13 IO Pull Down General-purpose IO
QSPI for Serial Flash QSPI_CS P8 O Pull Up Chip-select output from the device. Device is a master connected to serial flash slave.
QSPI_CLK R10 O Pull Down Clock output from the device. Device is a master connected to serial flash slave.
QSPI[0] R11 IO Pull Down Data IN/OUT
QSPI[1] P9 IO Pull Down Data IN/OUT
QSPI[2] R12 IO Pull Up Data IN/OUT
QSPI[3] P10 IO Pull Up Data IN/OUT
Flash programming and RS232 UART RS232_TX N6 O Pull Down UART pins for programming external flash
RS232_RX N5 I Pull Up
Test and Debug output for preproduction phase. Can be pinned out on production hardware for field debug Analog Test1 P1 IO Internal test signal
Analog Test2 P2 IO Internal test signal
Analog Test3 P3 IO Internal test signal
Analog Test4 R2 IO Internal test signal
ANAMUX C13 IO Internal test signal
VSENSE C14 IO Internal test signal
Status of PULL structures associated with the IO after device POWER UP.
Cascading feature is available only in the AWR1243P variant.
For the AWR1243 WARM_RESET can be used as an output only pin for status indication.