SLUS968G January   2010  – August 2015

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Options
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Dissipation Ratings
    6. 8.6 Electrical Characteristics
    7. 8.7 Typical Characteristics
      1. 8.7.1 Power Up, Power Down, OVP, Disable and Enable Waveforms
      2. 8.7.2 Protection Circuits Waveforms
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Down or Undervoltage Lockout (UVLO)
      2. 9.3.2  UVLO
      3. 9.3.3  Power-Up
      4. 9.3.4  Sleep Mode
      5. 9.3.5  New Charge Cycle
      6. 9.3.6  Overvoltage-Protection (OVP) - Continuously Monitored
      7. 9.3.7  Power Good Indication (PG)
      8. 9.3.8  CHG Pin Indication
      9. 9.3.9  CHG and PG LED Pull-Up Source
      10. 9.3.10 IN-DPM (VIN-DPM or IN-DPM)
      11. 9.3.11 OUT
      12. 9.3.12 ISET
      13. 9.3.13 PRE_TERM - Pre-Charge and Termination Programmable Threshold
      14. 9.3.14 ISET2
      15. 9.3.15 TS
    4. 9.4 Device Functional Modes
      1. 9.4.1 Termination and Timer Disable Mode (TTDM) -TS Pin High
      2. 9.4.2 Timers
      3. 9.4.3 Termination
      4. 9.4.4 Battery Detect Routine
      5. 9.4.5 Refresh Threshold
      6. 9.4.6 Starting a Charge on a Full Battery
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Calculations
          1. 10.2.2.1.1 Program the Fast Charge Current, ISET:
          2. 10.2.2.1.2 Program the Termination Current Threshold, ITERM:
          3. 10.2.2.1.3 TS Function
          4. 10.2.2.1.4 CHG and PG
        2. 10.2.2.2 Selecting IN and OUT Pin Capacitors
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
      1. 12.3.1 Leakage Current Effects on Battery Capacity
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Specifications

8.1 Absolute Maximum Ratings(1)

over operating free-air temperature (unless otherwise noted)
MIN MAX UNIT
Input Voltage(2) IN (with respect to VSS) –0.3 12 V
OUT (with respect to VSS) –0.3 7 V
PRE-TERM, ISET, ISET2, TS, CHG, PG, ASI, ASO
(with respect to VSS)
–0.3 7 V
Input Current IN 1.25 A
Output Current (Continuous) OUT 1.25 A
Output Sink Current CHG 15 mA
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions(1)

MIN MAX UNIT
VIN IN voltage range 3.5 12 V
IN operating voltage range, Restricted by VDPM and VOVP 4.45 6.45 V
IIN Input current, IN pin 1.0 A
IOUT Current, OUT pin 1.0 A
TJ Junction temperature 0 125 °C
RPRE-TERM Programs precharge and termination current thresholds 1 10
RISET Fast-charge current programming resistor 0.540 49.9
RTS 10kΩ NTC thermistor range without entering BAT_EN or TTDM 1.66 258
(1) Operation with VIN less than 4.5V or in drop-out may result in reduced performance.

8.4 Thermal Information

THERMAL METRIC(1) bq2409x UNIT
DGQ
10 PINS
RθJA Junction-to-ambient thermal resistance 71.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.9
RθJB Junction-to-board thermal resistance 45.2
ψJT Junction-to-top characterization parameter 3.5
ψJB Junction-to-board characterization parameter 44.9
RθJC(bot) Junction-to-case (bottom) thermal resistance 19.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Dissipation Ratings(1)(2)

PACKAGE RθJA RθJC TA ≤ 25°C
POWER RATING
DERATING FACTOR
TA > 25°C
5x3mm MSOP 52°C/W 48°C/W 1.92 W 19.2 mW/°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is connected to the ground plane by a 2×3 via matrix

8.6 Electrical Characteristics

over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
UVLO Undervoltage lock-out Exit VIN: 0V → 4V Update based on sim/char 3.15 3.3 3.45 V
VHYS_UVLO Hysteresis on VUVLO_RISE falling VIN: 4V→0V,
VUVLO_FALL = VUVLO_RISE –VHYS-UVLO
175 227 280 mV
VIN-DT Input power good detection threshold is VOUT + VIN-DT (Input power good if VIN > VOUT + VIN-DT);
VOUT = 3.6V, VIN: 3.5V → 4V
30 80 145 mV
VHYS-INDT Hysteresis on VIN-DT falling VOUT = 3.6V, VIN: 4V → 3.5V 31 mV
tDGL(PG_PWR) Deglitch time on exiting sleep. Time measured from VIN: 0V → 5V 1μs rise-time to PG = low, VOUT = 3.6V 45 μs
tDGL(PG_NO-PWR) Deglitch time on VHYS-INDT power down. Same as entering sleep. Time measured from VIN: 5V → 3.2V 1μs fall-time to PG = OC, VOUT = 3.6V 29 ms
VOVP Input over-voltage protection threshold VIN: 5V → 7V 6.5 6.65 6.8 V
tDGL(OVP-SET) Input over-voltage blanking time VIN: 5V → 7V 113 μs
VHYS-OVP Hysteresis on OVP VIN: 7V → 5V 95 mV
tDGL(OVP-REC) Deglitch time exiting OVP Time measured from VIN: 7V → 5V 1μs fall-time to PG = LO 30 μs
VIN-DPM USB/Adaptor low input voltage protection. Restricts lout at VIN-DPM Feature active in USB mode; Limit Input Source Current to 50mA; VOUT = 3.5V; RISET = 825Ω 4.34 4.4 4.46 V
Feature active in Adaptor mode; Limit Input Source Current to 50mA; VOUT = 3.5V; RISET = 825Ω 4.24 4.3 4.36
IIN-USB-CL USB input I-Limit 100mA ISET2 = Float; RISET = 825Ω 85 92 100 mA
USB input I-Limit 500mA ISET2 = High; RISET = 825Ω 430 462 500
ISET SHORT CIRCUIT TEST
RISET_SHORT Highest Resistor value considered a fault (short). Monitored for Iout>90mA Riset: 600Ω → 250Ω, IOUT latches off. Cycle power to Reset. 280 500 Ω
tDGL_SHORT Deglitch time transition from ISET short to Iout disable Clear fault by cycling IN or TS/BAT_EN 1 ms
IOUT_CL Maximum OUT current limit Regulation (Clamp) VIN = 5V, VOUT = 3.6V, VISET2 = Low, RISET:
600Ω → 250Ω, Iout latches off after tDGL-SHORT
1.05 1.4 A
BATTERY SHORT PROTECTION
VOUT(SC) OUT pin short-circuit detection threshold/ precharge threshold VOUT:3V → 0.5V, no deglitch 0.75 0.8 0.85 V
VOUT(SC-HYS) OUT pin Short hysteresis Recovery ≥ VOUT(SC) + VOUT(SC-HYS); Rising, no Deglitch 77 mV
IOUT(SC) Source current to OUT pin during short-circuit detection 10 15 20 mA
QUIESCENT CURRENT
IOUT(PDWN) Battery current into OUT pin VIN = 0V 1 μA
IOUT(DONE) OUT pin current, charging terminated VIN = 6V, VOUT > VOUT(REG) 6
IIN(STDBY) Standby current into IN pin TS = LO, VIN ≤ 6V 125 μA
ICC Active supply current, IN pin TS = open, VIN = 6V, TTDM – no load on OUT pin, VOUT > VOUT(REG), IC enabled 0.8 1.0 mA
BATTERY CHARGER FAST-CHARGE
VOUT(REG) Battery regulation voltage (bq24090/1/2/3) VIN = 5.5V, IOUT = 25mA, (VTS-45°C≤ VTS ≤ VTS-0°C) 4.16 4.2 4.23 V
Battery regulation voltage (bq24095) VIN = 5.5V, IOUT = 25mA 4.30 4.35 4.40
VO_HT(REG) Battery hot regulation Voltage, bq24092/3 VIN = 5.5V, IOUT = 25mA, VTS-60°C≤ VTS ≤ VTS-45°C 4.02 4.06 4.1 V
IOUT(RANGE) Programmed Output “fast charge” current range VOUT(REG) > VOUT > VLOWV; VIN = 5V, ISET2=Lo,
RISET = 540 to 10.8kΩ
10 1000 mA
VDO(IN-OUT) Drop-Out, VIN – VOUT Adjust VIN down until IOUT = 0.5A, VOUT = 4.15V, RISET = 540 , ISET2=Lo (adaptor mode); TJ ≤ 100°C 325 520 mV
IOUT Output “fast charge” formula VOUT(REG) > VOUT > VLOWV; VIN = 5V, ISET2 = Lo KISET/RISET A
KISET Fast charge current factor for
bq24090, 91, 92, 93
RISET = KISET /IOUT; 50 < IOUT < 1000 mA 510 540 565
RISET = KISET /IOUT; 25 < IOUT < 50 mA 480 527 580
RISET = KISET /IOUT; 10 < IOUT < 25 mA 350 520 680
KISET Fast charge current factor for
bq24095
RISET = KISET /IOUT; 50 < IOUT < 1000 mA 510 560 585
RISET = KISET /IOUT; 25 < IOUT < 50 mA 480 557 596
RISET = KISET /IOUT; 10 < IOUT < 25 mA 350 555 680
PRECHARGE – SET BY PRETERM PIN
VLOWV Pre-charge to fast-charge transition threshold 2.4 2.5 2.6 V
tDGL1(LOWV) Deglitch time on pre-charge to fast-charge transition 70 μs
tDGL2(LOWV) Deglitch time on fast-charge to pre-charge transition 32 ms
IPRE-TERM Refer to the Termination Section
%PRECHG Pre-charge current, default setting VOUT < VLOWV; RISET = 1080Ω;
RPRE-TERM= High Z
18 20 22 %IOUT-CC
Pre-charge current formula RPRE-TERM = KPRE-CHG (Ω/%) × %PRE-CHG (%) RPRE-TERM/KPRE-CHG%
KPRE-CHG % Pre-charge Factor VOUT < VLOWV, VIN = 5V, RPRE-TERM = 2k to 10kΩ; RISET = 1080Ω , RPRE-TERM = KPRE-CHG × %IFAST-CHG, where %IFAST-CHG is 20 to 100% 90 100 110 Ω/%
VOUT < VLOWV, VIN = 5V, RPRE-TERM = 1k to 2kΩ; RISET = 1080Ω, RPRE-TERM = KPRE-CHG × %IFAST-CHG, where %IFAST-CHG is 10% to 20% 84 100 117 Ω/%
TERMINATION – SET BY PRE-TERM PIN
%TERM Termination Threshold Current, default setting VOUT > VRCH; RISET = 1k;
RPRE-TERM= High Z
9 10 11 %IOUT-CC
Termination Current Threshold Formula RPRE-TERM = KTERM (Ω/%) × %TERM (%) RPRE-TERM/ KTERM
KTERM % Term Factor VOUT > VRCH, VIN = 5V, RPRE-TERM = 2k to 10kΩ ; RISET = 750Ω KTERM × %IFAST-CHG, where %IFAST-CHG is 10 to 50% 182 200 216 Ω/%
VOUT > VRCH, VIN = 5V, RPRE-TERM = 1k to 2kΩ ; RISET = 750Ω KTERM × %Iset, where %Iset is 5 to 10% 174 199 224
IPRE-TERM Current for programming the term. and pre-chg with resistor. ITerm-Start is the initial PRE-TERM current. RPRE-TERM = 2k, VOUT = 4.15V 71 75 81 μA
%TERM Termination current formula RTERM/ KTERM%
tDGL(TERM) Deglitch time, termination detected 29 ms
ITerm-Start Elevated PRE-TERM current for, tTerm-Start, during start of charge to prevent recharge of full battery, 80 85 92 μA
tTerm-Start Elevated termination threshold initially active for tTerm-Start 1.25 min
RECHARGE OR REFRESH
VRCH Recharge detection threshold – Normal Temp VIN = 5V, VTS = 0.5V, VOUT: 4.25V → VRCH VO(REG)-0.120 VO(REG)-0.095 VO(REG)-0.070 V
Recharge detection threshold – Hot Temp VIN = 5V, VTS = 0.2V, VOUT: 4.15V → VRCH VO(REG)-0.130 VO(REG)-0.105 VO(REG)-0.080 V
tDGL1(RCH) Deglitch time, recharge threshold detected VIN = 5V, VTS = 0.5V, VOUT: 4.25V → 3.5V in 1μs; tDGL(RCH) is time to ISET ramp 29 ms
tDGL2(RCH) Deglitch time, recharge threshold detected in OUT-Detect Mode VIN = 5V, VTS = 0.5V, VOUT = 3.5V inserted; tDGL(RCH) is time to ISET ramp 3.6 ms
BATTERY DETECT ROUTINE
VREG-BD VOUT Reduced regulation during battery detect VIN = 5V, VTS = 0.5V, Battery Absent VO(REG)-0.450 VO(REG)-0.400 VO(REG)-350 V
IBD-SINK Sink current during VREG-BD 7 10 mA
tDGL(HI/LOW REG) Regulation time at VREG or VREG-BD 25 ms
VBD-HI High battery detection threshold VIN = 5V, VTS = 0.5V, Battery Absent VO(REG) -0.150 VO(REG)-0.100 VO(REG)-0.050 V
VBD-LO Low battery detection threshold VIN = 5V, VTS = 0.5V, Battery Absent VREG-BD
+0.50
VREG-BD +0.1 VREG-BD
+0.15
V
BATTERY CHARGING TIMERS AND FAULT TIMERS
tPRECHG Pre-charge safety timer value Restarts when entering Pre-charge; Always enabled when in pre-charge. 1700 1940 2250 s
tMAXCH Charge safety timer value Clears fault or resets at UVLO, TS/BAT_EN disable, OUT Short, exiting LOWV and Refresh 34000 38800 45000 s
BATTERY-PACK NTC MONITOR (Note 1); TS pin: 10k and 100k NTC
INTC-10k NTC bias current, bq24090/2/5 VTS = 0.3V 48 50 52 μA
INTC-100k NTC bias current, bq24091/3 VTS = 0.3V 4.8 5.0 5.2 μA
INTC-DIS-10k 10k NTC bias current when Charging is disabled, bq24090/2/5 VTS = 0V 27 30 34 μA
INTC-DIS-100k 100k NTC bias current when Charging is disabled, bq24091/3 VTS = 0V 4.4 5.0 5.8 μA
INTC-FLDBK-10k INTC is reduced prior to entering TTDM to keep cold thermistor from entering TTDM, bq24090/2/5 VTS: Set to 1.525V 4 5 6.5 μA
INTC-FLDBK-100k INTC is reduced prior to entering TTDM to keep cold thermistor from entering TTDM, bq24091/3 VTS: Set to 1.525V 1.1 1.5 1.9 μA
VTTDM(TS) Termination and timer disable mode Threshold – Enter VTS: 0.5V → 1.7V; Timer Held in Reset 1550 1600 1650 mV
VHYS-TTDM(TS) Hysteresis exiting TTDM VTS: 1.7V → 0.5V; Timer Enabled 100 mV
VCLAMP(TS) TS maximum voltage clamp VTS = Open (Float) 1800 1950 2000 mV
tDGL(TTDM) Deglitch exit TTDM between states 57 ms
Deglitch enter TTDM between states 8 μs
VTS_I-FLDBK TS voltage where INTC is reduce to keep thermistor from entering TTDM INTC adjustment (90 to 10%; 45 to 6.6uS) takes place near this spec threshold. VTS: 1.425V → 1.525V 1475 mV
CTS Optional Capacitance – ESD 0.22 μF
VTS-0°C Low temperature CHG Pending Low Temp Charging to Pending;
VTS: 1.0V → 1.5V
1205 1230 1255 mV
VHYS-0°C Hysteresis at 0°C Charge pending to low temp charging;
VTS: 1.5V → 1V
86 mV
VTS-10°C Low temperature, half charge, bq24092/3 Normal charging to low temp charging;
VTS: 0.5V → 1V
765 790 815 mV
VHYS-10°C Hysteresis at 10°C, bq24092/3 Low temp charging to normal CHG;
VTS: 1.0V → 0.5V
35 mV
VTS-45°C High temperature at 4.1V Normal charging to high temp CHG;
VTS: 0.5V → 0.2V
263 278 293 mV
VHYS-45°C Hysteresis at 45°C High temp charging to normal CHG;
VTS: 0.2V → 0.5V
10.7 mV
VTS-60°C High temperature Disable, bq24092/3 High temp charge to pending;
VTS: 0.2V → 0.1V
170 178 186 mV
VHYS-60°C Hysteresis at 60°C, bq24092/3 Charge pending to high temp CHG;
VTS: 0.1V → 0.2V
11.5 mV
tDGL(TS_10C) Deglitch for TS thresholds: 10C, bq24092/3 Normal to Cold Operation; VTS: 0.6V → 1V 50 ms
Cold to Normal Operation; VTS: 1V → 0.6V 12
tDGL(TS) Deglitch for TS thresholds: 0/45/60C. Battery charging 30 ms
VTS-EN-10k Charge Enable Threshold, (10k NTC) VTS: 0V → 0.175V; 80 88 96 mV
VTS-DIS_HYS-10k HYS below VTS-EN-10k to Disable, (10k NTC) VTS: 0.125V → 0V; 12 mV
VTS-EN-100k Charge Enable Threshold, bq24090/2 VTS: 0V → 0.175V; 140 150 160 mV
VTS-DIS_HYS-100k HYS below VTS-EN-100k to Disable, bq24091/3 VTS: 0.125V → 0V; 50 mV
THERMAL REGULATION
TJ(REG) Temperature regulation limit 125 °C
TJ(OFF) Thermal shutdown temperature 155 °C
TJ(OFF-HYS) Thermal shutdown hysteresis 20 °C
LOGIC LEVELS ON ISET2
VIL Logic LOW input voltage Sink 8 μA 0.4 V
VIH Logic HIGH input voltage Source 8 μA 1.4 V
IIL Sink current required for LO VISET2= 0.4V 2 9 μA
IIH Source current required for HI VISET2= 1.4V 1.1 8 μA
VFLT ISET2 Float Voltage 575 900 1225 mV
LOGIC LEVELS ON CHG AND PG
VOL Output LOW voltage ISINK = 5 mA 0.4 V
ILEAK Leakage current into IC VCHG = 5V, VPG = 5V 1 μA

8.7 Typical Characteristics

SETUP: bq2409x typical applications schematic; VIN = 5V, VBAT = 3.6V (unless otherwise indicated)

8.7.1 Power Up, Power Down, OVP, Disable and Enable Waveforms

bq24091 bq24092 bq24093 bq24095 bq24090 pg_chg_lus941.gifFigure 1. OVP 8V Adaptor - Hot Plug
bq24091 bq24092 bq24093 bq24095 bq24090 ena_dis_lus941.gif
10kΩ resistor from TS to GND.
10kΩ is shorted to disable the IC.
Figure 3. TS Enable and Disable
bq24091 bq24092 bq24093 bq24095 bq24090 gnd_rem_lus941.gifFigure 5. Battery Removal – GND Removed 1st, 42 Ω Load
bq24091 bq24092 bq24093 bq24095 bq24090 step_chg_lus941.gifFigure 2. OVP from Normal Power-Up
Operation – VIN 0V → 5V → 6.8V → 5V
bq24091 bq24092 bq24093 bq24095 bq24090 no_batt_lus941.gif
Fixed 10kΩ resistor, between TS and GND.
Figure 4. Hot Plug Source w/ No Battery –
Battery Detection
bq24091 bq24092 bq24093 bq24095 bq24090 ts_dis_cnt_lus941.gifFigure 6. Battery Removal With OUT and
TS Disconnect 1st, With 100 Ω Load

8.7.2 Protection Circuits Waveforms

bq24091 bq24092 bq24093 bq24095 bq24090 usb_pwrup_lus941.gif
CH4: Iout (0.2A/Div)
Figure 7. ISET Shorted Prior to USB Power-Up
bq24091 bq24092 bq24093 bq24095 bq24090 pwr_iout_lus941.gif
The IC temperature rises to 125°C and enters thermal regulation. Charge current is reduced to regulate the IC at 125°C. VIN is reduced, the IC temperature drops, the charge current returns to the programmed value.
Figure 9. Thermal Regulation – Vin increases PWR/Iout Reduced
bq24091 bq24092 bq24093 bq24095 bq24090 lo_hi_cur_lus940.gifFigure 11. KISET for Low and High Currents
bq24091 bq24092 bq24093 bq24095 bq24090 VO_vs_IO_SLUS968.gifFigure 13. Load Regulation – bq24095
bq24091 bq24092 bq24093 bq24095 bq24090 usb_limits_lus941.gif
Figure 8. DPM – USB Current Limits – Vin Regulated to 4.4V
bq24091 bq24092 bq24093 bq24095 bq24090 sleep_mode_lus941.gif
VIN swept from 5V to 3.9V to 5V
VBAT = 4V
Figure 10. Entering and Exiting Sleep Mode
bq24091 bq24092 bq24093 bq24095 bq24090 vo_io_lus940.gifFigure 12. Load Regulation Over Temperature