SLUSCB3 Data sheet

SLUSCB3 July 2015

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RSM|32
- MPQF195B

Thermal pad, mechanical data (Package|Pins)

RSM|32
- QFND239E

Orderable Information

11 Layout

11.1 Layout Guidelines

A battery fuel gauge circuit board is a challenging environment due to the fundamental incompatibility of high-current traces and ultra-low current semiconductor devices. The best way to protect against unwanted trace-to-trace coupling is with a component placement, such as that shown in Figure 43, where the high-current section is on the opposite side of the board from the electronic devices. Clearly this is not possible in many situations due to mechanical constraints. Still, every attempt should be made to route high-current traces away from signal traces, which enter the bq40z50-R1 directly. IC references and registers can be disturbed and in rare cases damaged due to magnetic and capacitive coupling from the high-current path. Note that during surge current and ESD events, the high-current traces appear inductive and can couple unwanted noise into sensitive nodes of the gas gauge electronics, as illustrated in Figure 44.

Figure 43. Separating High- and Low-Current Sections Provides an Advantage in Noise Immunity

Figure 44. Avoid Close Spacing Between High-Current and Low-Level Signal Lines

Kelvin voltage sensing is extremely important in order to accurately measure current and top and bottom cell voltages. Place all filter components as close as possible to the device. Route the traces from the sense resistor in parallel to the filter circuit. Adding a ground plane around the filter network can add additional noise immunity. Figure 45 and Figure 46 demonstrates correct kelvin current sensing.

Figure 45. Sensing Resistor PCB Layout

Figure 46. Sense Resistor, Ground Shield, and Filter Circuit Layout

11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors

The general principle is to use wide copper traces to lower the inductance of the bypass capacitor circuit. In Figure 47, an example layout demonstrates this technique.

Figure 47. Use Wide Copper Traces to Lower the Inductance of Bypass Capacitors C1, C2, and C3

11.1.2 ESD Spark Gap

Protect SMBus Clock, Data, and other communication lines from ESD with a spark gap at the connector. The pattern in Figure 48 recommended, with 0.2-mm spacing between the points.

Figure 48. Recommended Spark-Gap Pattern Helps Protect Communication Lines from ESD

11.2 Layout Example

Figure 49. Top Layer

bq40z50-R1 dev_internal_layer_1_SLUUAV7.gif

Figure 50. Internal Layer 1

bq40z50-R1 dev_internal_layer_2_SLUUAV7.gif

Figure 51. Internal Layer 2

Figure 52. Bottom Layer