SLUSDH3 December   2019 BQ76952

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     BQ76952 TQFP Package (PFB) Pin Functions
  6. Specifications
    1. Table 1.  Absolute Maximum Ratings
    2. Table 2.  ESD Ratings
    3. Table 3.  Recommended Operating Conditions
    4. Table 4.  Thermal Information bq76952
    5. Table 5.  Supply Current
    6. Table 6.  Digital I/O
    7. Table 7.  LD Pin
    8. Table 8.  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. Table 9.  FUSE Pin Functionality
    10. Table 10. Power-On Reset
    11. Table 11. REG18 LDO
    12. Table 12. REG0 Pre-regulator
    13. Table 13. REG1 LDO
    14. Table 14. REG2 LDO
    15. Table 15. Voltage References
    16. Table 16. Coulomb Counter
    17. Table 17. Coulomb Counter Digital Filter (CC1)
    18. Table 18. Current Measurement Digital Filter (CC2)
    19. Table 19. Current Wake Detector
    20. Table 20. Analog-to-Digital Converter
    21. Table 21. Cell Balancing
    22. Table 22. Cell Open Wire Detector
    23. Table 23. Internal Temperature Sensor
    24. Table 24. Thermistor Measurement
    25. Table 25. Internal Oscillators
    26. Table 26. High-side NFET Drivers
    27. Table 27. Comparator-Based Protection Subsystem
    28. Table 28. Timing Requirements - I2C Interface, 100 kHz Mode
    29. Table 29. Timing Requirements - I2C Interface, 400kHz Mode
    30. Table 30. Timing Requirements - HDQ Interface
    31. Table 31. Timing Requirements - SPI Interface
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Configuration - Direct Commands and Subcommands
      2. 7.3.2  Device Memory
        1. 7.3.2.1 Configuration Using OTP or Registers
      3. 7.3.3  Measurement System
        1. 7.3.3.1  Voltage Measurement
          1. 7.3.3.1.1 Voltage Measurement Schedule
          2. 7.3.3.1.2 Usage of VC Pins for Cells versus Interconnect
          3. 7.3.3.1.3 Cell Interconnect Resistance
        2. 7.3.3.2  General Purpose ADCIN Functionality
        3. 7.3.3.3  Coulomb Counter and Digital Filters
        4. 7.3.3.4  Synchronized Voltage and Current Measurement
        5. 7.3.3.5  Subcommands 0x0071 DASTATUS1(), 0x0072 DASTATUS2(), 0x0073 DASTATUS3(), and 0x0074 DASTATUS4() - Cell Voltage and Synchronized Current Counts
        6. 7.3.3.6  Subcommands 0x0075 DASTATUS5() and 0x0076 DASTATUS6() - Additional Voltage, Current, Charge, and Temperature Measurements
        7. 7.3.3.7  Internal Temperature Measurement
        8. 7.3.3.8  Thermistor Temperature Measurement
        9. 7.3.3.9  Factory Trim of Voltage ADC
        10. 7.3.3.10 Voltage Calibration (ADC Measurements)
        11. 7.3.3.11 Voltage Calibration (COV and CUV Protections)
        12. 7.3.3.12 Current Calibration
        13. 7.3.3.13 Temperature Calibration
      4. 7.3.4  Integrated Protection Subsystem
        1. 7.3.4.1  Protections
        2. 7.3.4.2  High-Side NFET Drivers
        3. 7.3.4.3  Cell Overvoltage Protection
        4. 7.3.4.4  Cell Undervoltage Protection
        5. 7.3.4.5  Short Circuit in Discharge Protection
        6. 7.3.4.6  Overcurrent in Charge Protection
        7. 7.3.4.7  Overcurrent in Discharge 1, 2, and 3 Protections
        8. 7.3.4.8  Overtemperature in Charge Protection
        9. 7.3.4.9  Overtemperature in Discharge Protection
        10. 7.3.4.10 Overtemperature FET Protection
        11. 7.3.4.11 Internal Overtemperature Protection
        12. 7.3.4.12 Undertemperature in Charge Protection
        13. 7.3.4.13 Undertemperature in Discharge Protection
        14. 7.3.4.14 Internal Undertemperature Protection
        15. 7.3.4.15 Host Watchdog Protection
        16. 7.3.4.16 Precharge Timeout Protection
        17. 7.3.4.17 Load Detect Functionality
        18. 7.3.4.18 Protection FETs
          1. 7.3.4.18.1 FET Configuration
          2. 7.3.4.18.2 FET Control
            1. 7.3.4.18.2.1 Precharge Mode
            2. 7.3.4.18.2.2 Predischarge Mode
      5. 7.3.5  Voltage References
      6. 7.3.6  ADC Multiplexer
      7. 7.3.7  LDOs
        1. 7.3.7.1 Pre-Regulator Control
        2. 7.3.7.2 REG1 and REG2 LDO Controls
      8. 7.3.8  Standalone Versus Host Interface
      9. 7.3.9  Multifunction Pin Controls
      10. 7.3.10 RST_SHUT Pin Operation
      11. 7.3.11 CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      12. 7.3.12 ALERT Pin Operation
      13. 7.3.13 DDSG and DCHG Pin Operation
      14. 7.3.14 Operational Modes
        1. 7.3.14.1 NORMAL Mode
        2. 7.3.14.2 SLEEP Mode
        3. 7.3.14.3 DEEPSLEEP Mode
        4. 7.3.14.4 SHUTDOWN Mode
        5. 7.3.14.5 CONFIG_UPDATE Mode
      15. 7.3.15 Permanent Fail
        1. 7.3.15.1  Copper Deposition (CUDEP) Permanent Fail
        2. 7.3.15.2  Safety Undervoltage (SUV) Permanent Fail
        3. 7.3.15.3  Safety Overvoltage (SOV) Permanent Fail
        4. 7.3.15.4  Safety Overcurrent in Charge (SOCC) Permanent Fail
        5. 7.3.15.5  Safety Overcurrent in Discharge (SOCD) Permanent Fail
        6. 7.3.15.6  Safety Cell Overtemperature (SOT) Permanent Fail
        7. 7.3.15.7  Safety FET Overtemperature (SOTF) Permanent Fail
        8. 7.3.15.8  Charge FET (CFETF) Permanent Fail
        9. 7.3.15.9  Discharge FET (DFETF) Permanent Fail
        10. 7.3.15.10 Secondary Protector (2LVL) Permanent Fail
        11. 7.3.15.11 Voltage Imbalance in Relax (VIMR) Permanent Fail
        12. 7.3.15.12 Voltage Imbalance in Active (VIMA) Permanent Fail
        13. 7.3.15.13 Short Circuit in Discharge Latched Permanent Fail
        14. 7.3.15.14 OTP Memory Signature Permanent Fail
        15. 7.3.15.15 Data ROM Memory Signature Permanent Fail
        16. 7.3.15.16 Instruction ROM Memory Signature Permanent Fail
        17. 7.3.15.17 LFO Oscillator Permanent Fail
        18. 7.3.15.18 VREF Permanent Fail
        19. 7.3.15.19 VSS Permanent Fail
        20. 7.3.15.20 Protection Comparator MUX Permanent Fail
        21. 7.3.15.21 Commanded Permanent Fail
        22. 7.3.15.22 Top of Stack Measurement Check
        23. 7.3.15.23 Cell Open Wire
      16. 7.3.16 Cell Balancing
      17. 7.3.17 Low Frequency Oscillator
      18. 7.3.18 High Frequency Oscillator
      19. 7.3.19 Device Security
      20. 7.3.20 0x00 Control Status() and 0x12 Battery Status() Commands
      21. 7.3.21 Fuse Drive
      22. 7.3.22 0x0070 MANU_DATA() Subcommand
      23. 7.3.23 Diagnostics
        1. 7.3.23.1 VREF2 Versus VREF1 Measurement
        2. 7.3.23.2 VSS Measurement
        3. 7.3.23.3 Top of Stack Measurement Check
        4. 7.3.23.4 LFO Oscillator Monitor
        5. 7.3.23.5 Protection Comparator Mux Check
        6. 7.3.23.6 Internal Watchdog Reset
        7. 7.3.23.7 Internal Memory Checks
      24. 7.3.24 Serial Communications Interfaces
        1. 7.3.24.1 I2C Communications Subsystem
        2. 7.3.24.2 SPI Communications Interface
          1. 7.3.24.2.1 SPI Protocol
        3. 7.3.24.3 HDQ Communications Interface
    4. 7.4 Data Formats
      1. 7.4.1 Unsigned Integer
      2. 7.4.2 Integer
      3. 7.4.3 Floating Point
      4. 7.4.4 Hex
    5. 7.5 Commands and Subcommands
      1. 7.5.1 Bitfield Definitions for Direct Commands
        1. 7.5.1.1  Control Status(): 0x00
          1. Table 72. Control Status Register Field Descriptions
        2. 7.5.1.2  Safety Alert A(): 0x02
          1. Table 73. Safety Alert A Register Field Descriptions
        3. 7.5.1.3  Safety Status A(): 0x03
          1. Table 74. Safety Status A Register Field Descriptions
        4. 7.5.1.4  Safety Alert B(): 0x04
          1. Table 75. Safety Alert B Register Field Descriptions
        5. 7.5.1.5  Safety Status B(): 0x05
          1. Table 76. Safety Status B Register Field Descriptions
        6. 7.5.1.6  Safety Alert C(): 0x06
          1. Table 77. Safety Alert C Register Field Descriptions
        7. 7.5.1.7  Safety Status C(): 0x07
          1. Table 78. Safety Status C Register Field Descriptions
        8. 7.5.1.8  PF Alert A(): 0x0A
          1. Table 79. PF Alert A Register Field Descriptions
        9. 7.5.1.9  PF Status A(): 0x0B
          1. Table 80. PF Status A Register Field Descriptions
        10. 7.5.1.10 PF Alert B(): 0x0C
          1. Table 81. PF Alert B Register Field Descriptions
        11. 7.5.1.11 PF Status B(): 0x0D
          1. Table 82. PF Status B Register Field Descriptions
        12. 7.5.1.12 PF Alert C(): 0x0E
          1. Table 83. PF Alert C Register Field Descriptions
        13. 7.5.1.13 PF Status C(): 0x0F
          1. Table 84. PF Status C Register Field Descriptions
        14. 7.5.1.14 PF Alert D(): 0x10
          1. Table 85. PF Alert D Register Field Descriptions
        15. 7.5.1.15 PF Status D(): 0x11
          1. Table 86. PF Status D Register Field Descriptions
        16. 7.5.1.16 Battery Status(): 0x12
          1. Table 87. Battery Status Register Field Descriptions
        17. 7.5.1.17 Alarm Status(): 0x62
          1. Table 88. Alarm Status Register Field Descriptions
        18. 7.5.1.18 Alarm Raw Status(): 0x64
          1. Table 89. Alarm Raw Status Register Field Descriptions
        19. 7.5.1.19 Alarm Enable(): 0x66
          1. Table 90. Alarm Enable Register Field Descriptions
        20. 7.5.1.20 FET Status(): 0x7F
          1. Table 91. FET Status Register Field Descriptions
      2. 7.5.2 Bitfield Definitions for Subcommands
        1. 7.5.2.1 0x0053 PF_STATUS[0]: PF Status A()
          1. Table 92. PF Status A Register Field Descriptions
        2. 7.5.2.2 0x0053 PF_STATUS[1]: PF Status B()
          1. Table 93. PF Status B Register Field Descriptions
        3. 7.5.2.3 0x0053 PF_STATUS[2]: PF Status C()
          1. Table 94. PF Status C Register Field Descriptions
        4. 7.5.2.4 0x0053 PF_STATUS[3]: PF Status D()
          1. Table 95. PF Status D Register Field Descriptions
        5. 7.5.2.5 0x0057 MANUFACTURINGSTATUS[0–1]: Manufacturing Status()
          1. Table 96. Manufacturing Status Register Field Descriptions
        6. 7.5.2.6 0x0097 FET_CONTROL[0]: FET Control()
          1. Table 97. FET Control Register Field Descriptions
        7. 7.5.2.7 0x0098 REG12_CONTROL[0]: REG12 Control()
          1. Table 98. REG12 Control Register Field Descriptions
        8. 7.5.2.8 0x00A0 OTP_WR_CHECK[0]: OTP Write Check Result()
          1. Table 99. OTP Write Check Result Register Field Descriptions
        9. 7.5.2.9 0x00A1 OTP_WRITE[0]: OTP Write Result()
          1. Table 100. OTP Write Result Register Field Descriptions
    6. 7.6 Data Memory Settings
      1. 7.6.1 Calibration
        1. 7.6.1.1  Calibration:Voltage
          1. 7.6.1.1.1  Calibration:Voltage:Cell 1 Gain
          2. 7.6.1.1.2  Calibration:Voltage:Cell 2 Gain
          3. 7.6.1.1.3  Calibration:Voltage:Cell 3 Gain
          4. 7.6.1.1.4  Calibration:Voltage:Cell 4 Gain
          5. 7.6.1.1.5  Calibration:Voltage:Cell 5 Gain
          6. 7.6.1.1.6  Calibration:Voltage:Cell 6 Gain
          7. 7.6.1.1.7  Calibration:Voltage:Cell 7 Gain
          8. 7.6.1.1.8  Calibration:Voltage:Cell 8 Gain
          9. 7.6.1.1.9  Calibration:Voltage:Cell 9 Gain
          10. 7.6.1.1.10 Calibration:Voltage:Cell 10 Gain
          11. 7.6.1.1.11 Calibration:Voltage:Cell 11 Gain
          12. 7.6.1.1.12 Calibration:Voltage:Cell 12 Gain
          13. 7.6.1.1.13 Calibration:Voltage:Cell 13 Gain
          14. 7.6.1.1.14 Calibration:Voltage:Cell 14 Gain
          15. 7.6.1.1.15 Calibration:Voltage:Cell 15 Gain
          16. 7.6.1.1.16 Calibration:Voltage:Cell 16 Gain
          17. 7.6.1.1.17 Calibration:Voltage:Pack Gain
          18. 7.6.1.1.18 Calibration:Voltage:TOS Gain
          19. 7.6.1.1.19 Calibration:Voltage:LD Gain
          20. 7.6.1.1.20 Calibration:Voltage:ADC Gain
        2. 7.6.1.2  Calibration:Current
          1. 7.6.1.2.1 Calibration:Current:CC Gain
          2. 7.6.1.2.2 Calibration:Current:Capacity Gain
        3. 7.6.1.3  Calibration:Vcell Offset
          1. 7.6.1.3.1 Calibration:Vcell Offset:Vcell Offset
        4. 7.6.1.4  Calibration:V Divider Offset
          1. 7.6.1.4.1 Calibration:V Divider Offset:Vdiv Offset
        5. 7.6.1.5  Calibration:Current Offset
          1. 7.6.1.5.1 Calibration:Current Offset:Coulomb Counter Offset Samples
          2. 7.6.1.5.2 Calibration:Current Offset:Board Offset
        6. 7.6.1.6  Calibration:Temperature
          1. 7.6.1.6.1  Calibration:Temperature:Internal Temp Offset
          2. 7.6.1.6.2  Calibration:Temperature:CFETOFF Temp Offset
          3. 7.6.1.6.3  Calibration:Temperature:DFETOFF Temp Offset
          4. 7.6.1.6.4  Calibration:Temperature:ALERT Temp Offset
          5. 7.6.1.6.5  Calibration:Temperature:TS1 Temp Offset
          6. 7.6.1.6.6  Calibration:Temperature:TS2 Temp Offset
          7. 7.6.1.6.7  Calibration:Temperature:TS3 Temp Offset
          8. 7.6.1.6.8  Calibration:Temperature:HDQ Temp Offset
          9. 7.6.1.6.9  Calibration:Temperature:DCHG Temp Offset
          10. 7.6.1.6.10 Calibration:Temperature:DDSG Temp Offset
        7. 7.6.1.7  Calibration:Internal Temp Model
          1. 7.6.1.7.1 Calibration:Internal Temp Model:Int Gain
          2. 7.6.1.7.2 Calibration:Internal Temp Model:Int base offset
          3. 7.6.1.7.3 Calibration:Internal Temp Model:Int Maximum AD
          4. 7.6.1.7.4 Calibration:Internal Temp Model:Int Maximum Temp
        8. 7.6.1.8  Calibration:18K Temperature Model
          1. 7.6.1.8.1  Calibration:18K Temperature Model:Coeff a1
          2. 7.6.1.8.2  Calibration:18K Temperature Model:Coeff a2
          3. 7.6.1.8.3  Calibration:18K Temperature Model:Coeff a3
          4. 7.6.1.8.4  Calibration:18K Temperature Model:Coeff a4
          5. 7.6.1.8.5  Calibration:18K Temperature Model:Coeff a5
          6. 7.6.1.8.6  Calibration:18K Temperature Model:Coeff b1
          7. 7.6.1.8.7  Calibration:18K Temperature Model:Coeff b2
          8. 7.6.1.8.8  Calibration:18K Temperature Model:Coeff b3
          9. 7.6.1.8.9  Calibration:18K Temperature Model:Coeff b4
          10. 7.6.1.8.10 Calibration:18K Temperature Model:Adc0
        9. 7.6.1.9  Calibration:180K Temperature Model
          1. 7.6.1.9.1  Calibration:180K Temperature Model:Coeff a1
          2. 7.6.1.9.2  Calibration:180K Temperature Model:Coeff a2
          3. 7.6.1.9.3  Calibration:180K Temperature Model:Coeff a3
          4. 7.6.1.9.4  Calibration:180K Temperature Model:Coeff a4
          5. 7.6.1.9.5  Calibration:180K Temperature Model:Coeff a5
          6. 7.6.1.9.6  Calibration:180K Temperature Model:Coeff b1
          7. 7.6.1.9.7  Calibration:180K Temperature Model:Coeff b2
          8. 7.6.1.9.8  Calibration:180K Temperature Model:Coeff b3
          9. 7.6.1.9.9  Calibration:180K Temperature Model:Coeff b4
          10. 7.6.1.9.10 Calibration:180K Temperature Model:Adc0
        10. 7.6.1.10 Calibration:Custom Temperature Model
          1. 7.6.1.10.1  Calibration:Custom Temperature Model:Coeff a1
          2. 7.6.1.10.2  Calibration:Custom Temperature Model:Coeff a2
          3. 7.6.1.10.3  Calibration:Custom Temperature Model:Coeff a3
          4. 7.6.1.10.4  Calibration:Custom Temperature Model:Coeff a4
          5. 7.6.1.10.5  Calibration:Custom Temperature Model:Coeff a5
          6. 7.6.1.10.6  Calibration:Custom Temperature Model:Coeff b1
          7. 7.6.1.10.7  Calibration:Custom Temperature Model:Coeff b2
          8. 7.6.1.10.8  Calibration:Custom Temperature Model:Coeff b3
          9. 7.6.1.10.9  Calibration:Custom Temperature Model:Coeff b4
          10. 7.6.1.10.10 Calibration:Custom Temperature Model:Rc0
          11. 7.6.1.10.11 Calibration:Custom Temperature Model:Adc0
        11. 7.6.1.11 Calibration:Current Deadband
          1. 7.6.1.11.1 Calibration:Current Deadband:Coulomb Counter Deadband
      2. 7.6.2 Settings
        1. 7.6.2.1  Settings:Fuse
          1. 7.6.2.1.1 Settings:Fuse:Min Blow Fuse Voltage
          2. 7.6.2.1.2 Settings:Fuse:Fuse Blow Timeout
        2. 7.6.2.2  Settings:Configuration
          1. 7.6.2.2.1  Settings:Configuration:Power Config
            1. Table 101. Power Config Register Field Descriptions
          2. 7.6.2.2.2  Settings:Configuration:REG12 Config
            1. Table 102. REG12 Config Register Field Descriptions
          3. 7.6.2.2.3  Settings:Configuration:REG0 Config
            1. Table 103. REG0 Config Register Field Descriptions
          4. 7.6.2.2.4  Settings:Configuration:HWD Regulator Options
            1. Table 104. HWD Regulator Options Register Field Descriptions
          5. 7.6.2.2.5  Settings:Configuration:Comm Type
          6. 7.6.2.2.6  Settings:Configuration:I2C Address
          7. 7.6.2.2.7  Settings:Configuration:Comm Idle Time
          8. 7.6.2.2.8  Settings:Configuration:CFETOFF Pin Config
            1. Table 105. CFETOFF Pin Config Register Field Descriptions
          9. 7.6.2.2.9  Settings:Configuration:DFETOFF Pin Config
            1. Table 106. DFETOFF Pin Config Register Field Descriptions
          10. 7.6.2.2.10 Settings:Configuration:ALERT Pin Config
            1. Table 107. ALERT Pin Config Register Field Descriptions
          11. 7.6.2.2.11 Settings:Configuration:TS1 Config
            1. Table 108. TS1 Config Register Field Descriptions
          12. 7.6.2.2.12 Settings:Configuration:TS2 Config
            1. Table 109. TS2 Config Register Field Descriptions
          13. 7.6.2.2.13 Settings:Configuration:TS3 Config
            1. Table 110. TS3 Config Register Field Descriptions
          14. 7.6.2.2.14 Settings:Configuration:HDQ Pin Config
            1. Table 111. HDQ Pin Config Register Field Descriptions
          15. 7.6.2.2.15 Settings:Configuration:DCHG Pin Config
            1. Table 112. DCHG Pin Config Register Field Descriptions
          16. 7.6.2.2.16 Settings:Configuration:DDSG Pin Config
            1. Table 113. DDSG Pin Config Register Field Descriptions
          17. 7.6.2.2.17 Settings:Configuration:DA Configuration
            1. Table 114. DA Configuration Register Field Descriptions
          18. 7.6.2.2.18 Settings:Configuration:Vcell Mode
            1. Table 115. Vcell Mode Register Field Descriptions
          19. 7.6.2.2.19 Settings:Configuration:CC3 Samples
        3. 7.6.2.3  Settings:Protection
          1. 7.6.2.3.1  Settings:Protection:Protection Configuration
            1. Table 116. Protection Configuration Register Field Descriptions
          2. 7.6.2.3.2  Settings:Protection:Enabled Protections A
            1. Table 117. Enabled Protections A Register Field Descriptions
          3. 7.6.2.3.3  Settings:Protection:Enabled Protections B
            1. Table 118. Enabled Protections B Register Field Descriptions
          4. 7.6.2.3.4  Settings:Protection:Enabled Protections C
            1. Table 119. Enabled Protections C Register Field Descriptions
          5. 7.6.2.3.5  Settings:Protection:CHG FET Protections A
            1. Table 120. CHG FET Protections A Register Field Descriptions
          6. 7.6.2.3.6  Settings:Protection:CHG FET Protections B
            1. Table 121. CHG FET Protections B Register Field Descriptions
          7. 7.6.2.3.7  Settings:Protection:CHG FET Protections C
            1. Table 122. CHG FET Protections C Register Field Descriptions
          8. 7.6.2.3.8  Settings:Protection:DSG FET Protections A
            1. Table 123. DSG FET Protections A Register Field Descriptions
          9. 7.6.2.3.9  Settings:Protection:DSG FET Protections B
            1. Table 124. DSG FET Protections B Register Field Descriptions
          10. 7.6.2.3.10 Settings:Protection:DSG FET Protections C
            1. Table 125. DSG FET Protections C Register Field Descriptions
          11. 7.6.2.3.11 Settings:Protection:Body Diode Threshold
        4. 7.6.2.4  Settings:Alarm
          1. 7.6.2.4.1 Settings:Alarm:Default Alarm Mask
            1. Table 126. Default Alarm Mask Register Field Descriptions
          2. 7.6.2.4.2 Settings:Alarm:SF Alert Mask A
          3. 7.6.2.4.3 Settings:Alarm:SF Alert Mask B
          4. 7.6.2.4.4 Settings:Alarm:SF Alert Mask C
          5. 7.6.2.4.5 Settings:Alarm:PF Alert Mask A
          6. 7.6.2.4.6 Settings:Alarm:PF Alert Mask B
          7. 7.6.2.4.7 Settings:Alarm:PF Alert Mask C
          8. 7.6.2.4.8 Settings:Alarm:PF Alert Mask D
        5. 7.6.2.5  Settings:Permanent Failure
          1. 7.6.2.5.1 Settings:Permanent Failure:Enabled PF A
            1. Table 127. Enabled PF A Register Field Descriptions
          2. 7.6.2.5.2 Settings:Permanent Failure:Enabled PF B
            1. Table 128. Enabled PF B Register Field Descriptions
          3. 7.6.2.5.3 Settings:Permanent Failure:Enabled PF C
            1. Table 129. Enabled PF C Register Field Descriptions
          4. 7.6.2.5.4 Settings:Permanent Failure:Enabled PF D
            1. Table 130. Enabled PF D Register Field Descriptions
        6. 7.6.2.6  Settings:FET
          1. 7.6.2.6.1 Settings:FET:FET Options
            1. Table 131. FET Options Register Field Descriptions
          2. 7.6.2.6.2 Settings:FET:Chg Pump Control
            1. Table 132. Chg Pump Control Register Field Descriptions
          3. 7.6.2.6.3 Settings:FET:Precharge Start Voltage
          4. 7.6.2.6.4 Settings:FET:Precharge Stop Voltage
          5. 7.6.2.6.5 Settings:FET:Predischarge Timeout
          6. 7.6.2.6.6 Settings:FET:Predischarge Stop Delta
        7. 7.6.2.7  Settings:Current Thresholds
          1. 7.6.2.7.1 Settings:Current Thresholds:Dsg Current Threshold
          2. 7.6.2.7.2 Settings:Current Thresholds:Chg Current Threshold
        8. 7.6.2.8  Settings:Cell Open-Wire
          1. 7.6.2.8.1 Settings:Cell Open-Wire:Check Time
        9. 7.6.2.9  Settings:Interconnect Resistances
          1. 7.6.2.9.1  Settings:Interconnect Resistances:Cell 1 Interconnect
          2. 7.6.2.9.2  Settings:Interconnect Resistances:Cell 2 Interconnect
          3. 7.6.2.9.3  Settings:Interconnect Resistances:Cell 3 Interconnect
          4. 7.6.2.9.4  Settings:Interconnect Resistances:Cell 4 Interconnect
          5. 7.6.2.9.5  Settings:Interconnect Resistances:Cell 5 Interconnect
          6. 7.6.2.9.6  Settings:Interconnect Resistances:Cell 6 Interconnect
          7. 7.6.2.9.7  Settings:Interconnect Resistances:Cell 7 Interconnect
          8. 7.6.2.9.8  Settings:Interconnect Resistances:Cell 8 Interconnect
          9. 7.6.2.9.9  Settings:Interconnect Resistances:Cell 9 Interconnect
          10. 7.6.2.9.10 Settings:Interconnect Resistances:Cell 10 Interconnect
          11. 7.6.2.9.11 Settings:Interconnect Resistances:Cell 11 Interconnect
          12. 7.6.2.9.12 Settings:Interconnect Resistances:Cell 12 Interconnect
          13. 7.6.2.9.13 Settings:Interconnect Resistances:Cell 13 Interconnect
          14. 7.6.2.9.14 Settings:Interconnect Resistances:Cell 14 Interconnect
          15. 7.6.2.9.15 Settings:Interconnect Resistances:Cell 15 Interconnect
          16. 7.6.2.9.16 Settings:Interconnect Resistances:Cell 16 Interconnect
        10. 7.6.2.10 Settings:Manufacturing
          1. 7.6.2.10.1 Settings:Manufacturing:Mfg Status Init
            1. Table 133. Mfg Status Init Register Field Descriptions
        11. 7.6.2.11 Settings:Cell Balancing Config
          1. 7.6.2.11.1 Settings:Cell Balancing Config:Balancing Configuration
            1. Table 134. Balancing Configuration Register Field Descriptions
          2. 7.6.2.11.2 Settings:Cell Balancing Config:Min Cell Temp
          3. 7.6.2.11.3 Settings:Cell Balancing Config:Max Cell Temp
          4. 7.6.2.11.4 Settings:Cell Balancing Config:Cell Balance Interval
          5. 7.6.2.11.5 Settings:Cell Balancing Config:Cell Balance Min Cell V (Charge)
          6. 7.6.2.11.6 Settings:Cell Balancing Config:Cell Balance Min Delta (Charge)
          7. 7.6.2.11.7 Settings:Cell Balancing Config:Cell Balance Min Cell V (Relax)
          8. 7.6.2.11.8 Settings:Cell Balancing Config:Cell Balance Min Delta (Relax)
      3. 7.6.3 Power
        1. 7.6.3.1 Power:Shutdown
          1. 7.6.3.1.1 Power:Shutdown:Shutdown Cell Voltage
          2. 7.6.3.1.2 Power:Shutdown:Shutdown Stack Voltage
          3. 7.6.3.1.3 Power:Shutdown:Shutdown Temperature
          4. 7.6.3.1.4 Power:Shutdown:Shutdown Temperature Delay
          5. 7.6.3.1.5 Power:Shutdown:Charger Present Threshold
          6. 7.6.3.1.6 Power:Shutdown:FET Off Delay
          7. 7.6.3.1.7 Power:Shutdown:Shutdown Command Delay
          8. 7.6.3.1.8 Power:Shutdown:Auto Shutdown Time
          9. 7.6.3.1.9 Power:Shutdown:RAM Fail Shutdown Time
        2. 7.6.3.2 Power:Sleep
          1. 7.6.3.2.1 Power:Sleep:Sleep Current
          2. 7.6.3.2.2 Power:Sleep:Voltage Time
          3. 7.6.3.2.3 Power:Sleep:Wake Comparator Current
          4. 7.6.3.2.4 Power:Sleep:Sleep Hysteresis Time
          5. 7.6.3.2.5 Power:Sleep:Sleep Charger Voltage Threshold
          6. 7.6.3.2.6 Power:Sleep:Sleep Charger PACK-TOS Delta
      4. 7.6.4 System Data
        1. 7.6.4.1 System Data:Integrity
          1. 7.6.4.1.1 System Data:Integrity:Config RAM Signature
      5. 7.6.5 Protections
        1. 7.6.5.1  Protections:CUV
          1. 7.6.5.1.1 Protections:CUV:Threshold
          2. 7.6.5.1.2 Protections:CUV:Delay
          3. 7.6.5.1.3 Protections:CUV:Recovery Hysteresis
        2. 7.6.5.2  Protections:COV
          1. 7.6.5.2.1 Protections:COV:Threshold
          2. 7.6.5.2.2 Protections:COV:Delay
          3. 7.6.5.2.3 Protections:COV:Recovery Hysteresis
        3. 7.6.5.3  Protections:COVL
          1. 7.6.5.3.1 Protections:COVL:Latch Limit
          2. 7.6.5.3.2 Protections:COVL:Counter Dec Delay
          3. 7.6.5.3.3 Protections:COVL:Recovery Time
        4. 7.6.5.4  Protections:OCC
          1. 7.6.5.4.1 Protections:OCC:Threshold
          2. 7.6.5.4.2 Protections:OCC:Delay
          3. 7.6.5.4.3 Protections:OCC:Recovery Threshold
          4. 7.6.5.4.4 Protections:OCC:PACK-TOS Delta
        5. 7.6.5.5  Protections:OCD1
          1. 7.6.5.5.1 Protections:OCD1:Threshold
          2. 7.6.5.5.2 Protections:OCD1:Delay
        6. 7.6.5.6  Protections:OCD2
          1. 7.6.5.6.1 Protections:OCD2:Threshold
          2. 7.6.5.6.2 Protections:OCD2:Delay
        7. 7.6.5.7  Protections:SCD
          1. 7.6.5.7.1 Protections:SCD:Threshold
          2. 7.6.5.7.2 Protections:SCD:Delay
          3. 7.6.5.7.3 Protections:SCD:Recovery Time
        8. 7.6.5.8  Protections:OCD3
          1. 7.6.5.8.1 Protections:OCD3:Threshold
          2. 7.6.5.8.2 Protections:OCD3:Delay
        9. 7.6.5.9  Protections:OCD
          1. 7.6.5.9.1 Protections:OCD:Recovery Threshold
        10. 7.6.5.10 Protections:OCDL
          1. 7.6.5.10.1 Protections:OCDL:Latch Limit
          2. 7.6.5.10.2 Protections:OCDL:Counter Dec Delay
          3. 7.6.5.10.3 Protections:OCDL:Recovery Time
          4. 7.6.5.10.4 Protections:OCDL:Recovery Threshold
        11. 7.6.5.11 Protections:SCDL
          1. 7.6.5.11.1 Protections:SCDL:Latch Limit
          2. 7.6.5.11.2 Protections:SCDL:Counter Dec Delay
          3. 7.6.5.11.3 Protections:SCDL:Recovery Time
          4. 7.6.5.11.4 Protections:SCDL:Recovery Threshold
        12. 7.6.5.12 Protections:OTC
          1. 7.6.5.12.1 Protections:OTC:Threshold
          2. 7.6.5.12.2 Protections:OTC:Delay
          3. 7.6.5.12.3 Protections:OTC:Recovery
        13. 7.6.5.13 Protections:OTD
          1. 7.6.5.13.1 Protections:OTD:Threshold
          2. 7.6.5.13.2 Protections:OTD:Delay
          3. 7.6.5.13.3 Protections:OTD:Recovery
        14. 7.6.5.14 Protections:OTF
          1. 7.6.5.14.1 Protections:OTF:Threshold
          2. 7.6.5.14.2 Protections:OTF:Delay
          3. 7.6.5.14.3 Protections:OTF:Recovery
        15. 7.6.5.15 Protections:OTINT
          1. 7.6.5.15.1 Protections:OTINT:Threshold
          2. 7.6.5.15.2 Protections:OTINT:Delay
          3. 7.6.5.15.3 Protections:OTINT:Recovery
        16. 7.6.5.16 Protections:UTC
          1. 7.6.5.16.1 Protections:UTC:Threshold
          2. 7.6.5.16.2 Protections:UTC:Delay
          3. 7.6.5.16.3 Protections:UTC:Recovery
        17. 7.6.5.17 Protections:UTD
          1. 7.6.5.17.1 Protections:UTD:Threshold
          2. 7.6.5.17.2 Protections:UTD:Delay
          3. 7.6.5.17.3 Protections:UTD:Recovery
        18. 7.6.5.18 Protections:UTINT
          1. 7.6.5.18.1 Protections:UTINT:Threshold
          2. 7.6.5.18.2 Protections:UTINT:Delay
          3. 7.6.5.18.3 Protections:UTINT:Recovery
        19. 7.6.5.19 Protections:Recovery
          1. 7.6.5.19.1 Protections:Recovery:Time
        20. 7.6.5.20 Protections:HWD
          1. 7.6.5.20.1 Protections:HWD:Delay
        21. 7.6.5.21 Protections:Load Detect
          1. 7.6.5.21.1 Protections:Load Detect:Active Time
          2. 7.6.5.21.2 Protections:Load Detect:Retry Delay
          3. 7.6.5.21.3 Protections:Load Detect:Timeout
        22. 7.6.5.22 Protections:PTO
          1. 7.6.5.22.1 Protections:PTO:Charge Threshold
          2. 7.6.5.22.2 Protections:PTO:Delay
          3. 7.6.5.22.3 Protections:PTO:Reset
      6. 7.6.6 Permanent Fail
        1. 7.6.6.1  Permanent Fail:CUDEP
          1. 7.6.6.1.1 Permanent Fail:CUDEP:Threshold
          2. 7.6.6.1.2 Permanent Fail:CUDEP:Delay
        2. 7.6.6.2  Permanent Fail:SUV
          1. 7.6.6.2.1 Permanent Fail:SUV:Threshold
          2. 7.6.6.2.2 Permanent Fail:SUV:Delay
        3. 7.6.6.3  Permanent Fail:SOV
          1. 7.6.6.3.1 Permanent Fail:SOV:Threshold
          2. 7.6.6.3.2 Permanent Fail:SOV:Delay
        4. 7.6.6.4  Permanent Fail:TOS
          1. 7.6.6.4.1 Permanent Fail:TOS:Threshold
          2. 7.6.6.4.2 Permanent Fail:TOS:Delay
        5. 7.6.6.5  Permanent Fail:SOCC
          1. 7.6.6.5.1 Permanent Fail:SOCC:Threshold
          2. 7.6.6.5.2 Permanent Fail:SOCC:Delay
        6. 7.6.6.6  Permanent Fail:SOCD
          1. 7.6.6.6.1 Permanent Fail:SOCD:Threshold
          2. 7.6.6.6.2 Permanent Fail:SOCD:Delay
        7. 7.6.6.7  Permanent Fail:SOT
          1. 7.6.6.7.1 Permanent Fail:SOT:Threshold
          2. 7.6.6.7.2 Permanent Fail:SOT:Delay
        8. 7.6.6.8  Permanent Fail:SOTF
          1. 7.6.6.8.1 Permanent Fail:SOTF:Threshold
          2. 7.6.6.8.2 Permanent Fail:SOTF:Delay
        9. 7.6.6.9  Permanent Fail:VIMR
          1. 7.6.6.9.1 Permanent Fail:VIMR:Check Voltage
          2. 7.6.6.9.2 Permanent Fail:VIMR:Max Relax Current
          3. 7.6.6.9.3 Permanent Fail:VIMR:Threshold
          4. 7.6.6.9.4 Permanent Fail:VIMR:Delay
          5. 7.6.6.9.5 Permanent Fail:VIMR:Relax Min Duration
        10. 7.6.6.10 Permanent Fail:VIMA
          1. 7.6.6.10.1 Permanent Fail:VIMA:Check Voltage
          2. 7.6.6.10.2 Permanent Fail:VIMA:Min Active Current
          3. 7.6.6.10.3 Permanent Fail:VIMA:Threshold
          4. 7.6.6.10.4 Permanent Fail:VIMA:Delay
        11. 7.6.6.11 Permanent Fail:CFETF
          1. 7.6.6.11.1 Permanent Fail:CFETF:OFF Threshold
          2. 7.6.6.11.2 Permanent Fail:CFETF:OFF Delay
        12. 7.6.6.12 Permanent Fail:DFETF
          1. 7.6.6.12.1 Permanent Fail:DFETF:OFF Threshold
          2. 7.6.6.12.2 Permanent Fail:DFETF:OFF Delay
        13. 7.6.6.13 Permanent Fail:VSSF
          1. 7.6.6.13.1 Permanent Fail:VSSF:Fail Threshold
          2. 7.6.6.13.2 Permanent Fail:VSSF:Delay
        14. 7.6.6.14 Permanent Fail:2LVL
          1. 7.6.6.14.1 Permanent Fail:2LVL:Delay
        15. 7.6.6.15 Permanent Fail:LFOF
          1. 7.6.6.15.1 Permanent Fail:LFOF:Delay
        16. 7.6.6.16 Permanent Fail:HWMX
          1. 7.6.6.16.1 Permanent Fail:HWMX:Delay
      7. 7.6.7 Security
        1. 7.6.7.1 Security:Settings
          1. 7.6.7.1.1 Security:Settings:Security Settings
            1. Table 135. Security Settings Register Field Descriptions
        2. 7.6.7.2 Security:Keys
          1. 7.6.7.2.1 Security:Keys:Unseal Key Step 1
          2. 7.6.7.2.2 Security:Keys:Unseal Key Step 2
          3. 7.6.7.2.3 Security:Keys:Full Access Key Step 1
          4. 7.6.7.2.4 Security:Keys:Full Access Key Step 2
      8. 7.6.8 Data Memory Summary
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Calibration Process
    3. 8.3 Unused Pins
    4. 8.4 Device Event Timing
  9. Power Supply Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Circuit Operation Instability
      2. 11.1.2 Unexpected Watchdog Resets
      3. 11.1.3 Cell Balancing Not Working Properly
      4. 11.1.4 Thermistor Pin Stays Biased After Measurement
      5. 11.1.5 Occasional Watchdog Reset when Exiting CONFIG_UPDATE Mode
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Battery monitoring capability for 3-series to 16-series cells
  • Integrated charge pump for high-side NFET protection with optional autonomous recovery
  • Extensive protection suite including voltage, temperature, current, and internal diagnostics
  • Two independent ADCs
    • Support for simultaneous current and voltage sampling
    • High-accuracy coulomb counter with input offset error < 1 µV (typical)
    • High accuracy cell voltage measurement < 10 mV (typical)
  • Wide-range current applications (±200-mV measurement range across sense resistor)
  • Integrated secondary chemical fuse drive protection
  • Autonomous or host-controlled cell balancing
  • Multiple power modes (typical battery pack operating range conditions)
    • NORMAL mode: 250 µA
    • Multiple SLEEP mode options: 20 µA to 60 µA
    • Multiple DEEPSLEEP mode options: 10 µA to 14 µA
    • SHUTDOWN Mode: < 2 µA
  • High voltage tolerance of 85 V on cell connect and select additional pins
  • Support for temperature sensing using internal sensor and up to 9 external thermistors
  • Integrated one-time-programmable (OTP) memory programmable by customers on production line
  • Communication options include 400-kHz I2C, SPI, and HDQ one-wire interface
  • Dual programmable LDOs for external system usage
  • 48-pin TQFP package (PFB)