SLUSDQ4 April 2019 BQ79606A-Q1
To ensure the best possible accuracy performance, TI recommends following some basic layout guidelines for the bq769606-Q1 to provide best EMI and BCI performance. The isolation caps must be placed close to the edge of the board. The Common Mode Chokes must be close to the daisy-chain cable connector to provide a high-impedance path to common-mode noise as it enters the board. Place the series resistors and TVS diodes next to the BQ79606A-Q1.
An unbroken ground plane layer as part of a four or more layer board is recommended, with all AVSS, CVSS, DVSS, and power pad connections made directly to the plane. The common GND planes, the cell balance 0 pin (CB0), and cell voltage sense 0 pin (VC0) are all three star connected directly to BAT0. There should also be a keep-out area on plane area adjacent to the isolation capacitors or transformers if daisy-chain communication is implemented. The following is a list of grounds.