SWRS161 December   2014 CC3100MOD


  1. 1Module Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 CC3100MOD Pin Diagram
    2. 3.2 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  Handling Ratings
    3. 4.3  Power-On Hours
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Brown-Out and Black-Outbrown-out and black-out section
    6. 4.6  Electrical Characteristics (3.3 V, 25°C)
    7. 4.7  Thermal Resistance Characteristics for MOB Package
    8. 4.8  Reset Requirement
    9. 4.9  Current Consumption
    10. 4.10 WLAN RF Characteristics
      1. 4.10.1 WLAN Transmitter Characteristics
    11. 4.11 Timing Characteristics
      1. 4.11.1 SPI Host Interface Timings
      2. 4.11.2 Wake-Up Sequence
      3. 4.11.3 Wakeup from Hibernatewakeup from hibernate table
      4. 4.11.4 Interfaces
        1. Host SPI Interface Timing
        2. SPI Host Interface
        3. Host UART
          1. 5-Wire UART Topology
          2. 4-Wire UART Topology
          3. 3-Wire UART Topology
  5. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Module Features
        1. WLAN
        2. Network Stack
        3. Host Interface and Driver
        4. System
    2. 5.2 Functional Block Diagram
    3. 5.3 Wi-Fi Network Processor Subsystem
    4. 5.4 Power-Management Subsystem
      1. 5.4.1 VBAT Wide-Voltage Connection
    5. 5.5 Low-Power Operating Modes
      1. 5.5.1 Low-Power Deep Sleep
      2. 5.5.2 Hibernate
  6. 6Applications, Implementation, and Layout
    1. 6.1 Reference Schematics
    2. 6.2 Bill of Materialsbill of materials
    3. 6.3 Layout Recommendations
      1. 6.3.1 RF Section (Placement and Routing)
      2. 6.3.2 Antenna Placement and Routing
      3. 6.3.3 Transmission Line
      4. 6.3.4 General Layout Recommendation
  7. 7Environmental Requirements and Specifications
    1. 7.1 Temperature
      1. 7.1.1 PCB Bending
    2. 7.2 Handling Environment
      1. 7.2.1 Terminals
      2. 7.2.2 Falling
    3. 7.3 Storage Condition
      1. 7.3.1 Moisture Barrier Bag Before Opened
      2. 7.3.2 Moisture Barrier Bag Open
    4. 7.4 Baking Conditions
    5. 7.5 Soldering and Reflow Condition
  8. 8Product and Documentation Support
    1. 8.1 Development Support
      1. 8.1.1 Firmware Updates
    2. 8.2 Device Nomenclature
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Export Control Notice
    7. 8.7 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Mechanical Drawing
    2. 9.2 Package Option
      1. 9.2.1 Packaging Information
        1. 9.2.2 Tape and Reel Information
      2. 9.2.2 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • MOB|63
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Specifications

4.1 Absolute Maximum Ratings

These specifications indicate levels where permanent damage to the module can occur. Functional operation is not ensured under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the module.
VBAT and VIO Respect to GND –0.5 3.3 3.8 V
Digital I/O Respect to GND –0.5 VBAT + 0.5 V
RF pins –0.5 2.1 V
Analog pins –0.5 2.1 V
Temperature –40 +85 °C

4.2 Handling Ratings

Tstg Storage temperature range –40 85 °C
VESD Electrostatic discharge (ESD) performance: Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) –1.0 1.0 kV
Charged device model (CDM),
per JESD22-C101(2)
All pins –250 250 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Power-On Hours

TAmbient up to 85°C, assuming 20% active mode and 80% sleep mode 17,500

4.4 Recommended Operating Conditions

Function operation is not ensured outside this limit, and operation outside this limit for extended periods can adversely affect long-term reliability of the module.(1)
VBAT and VIO Battery mode 2.3 3.3 3.6 V
Operating temperature –20 25 70 °C
Ambient thermal slew –20 20 °C/minute
(1) Operating temperature is limited by crystal frequency variation.
(2) To ensure WLAN performance, the ripple on the power supply must be less than ±300 mV.

4.5 Brown-Out and Black-Out

The module enters a brown-out condition whenever the input voltage dips below VBROWN (see Figure 4-1 and Figure 4-2). This condition must be considered during design of the power supply routing, especially if operating from a battery. High-current operations (such as a TX packet) cause a dip in the supply voltage, potentially triggering a brown-out. The resistance includes the internal resistance of the battery, contact resistance of the battery holder (4 contacts for a 2 x AA battery) and the wiring and PCB routing resistance.

Black_Brownout_Levels1_swas031.gifFigure 4-1 Brown-Out and Black-Out Levels (1 of 2)
Black_Brownout_Levels2_swas031.gifFigure 4-2 Brown-Out and Black-Out Levels (2 of 2)

In the brown-out condition, all sections of the CC3100MOD shut down within the module except for the Hibernate block (including the 32-kHz RTC clock), which remains on. The current in this state can reach approximately 400 µA.

The black-out condition is equivalent to a hardware reset event in which all states within the module are lost.

4.6 Electrical Characteristics (3.3 V, 25°C)

CIN Pin capacitance 4 pF
VIH High-level input voltage 0.65 × VDD VDD + 0.5 V V
VIL Low-level input voltage –0.5 0.35 × VDD V
IIH High-level input current 5 nA
IIL Low-level input current 5 nA
VOH High-level output voltage
(VDD = 3.0 V)
2.4 V
VOL Low-level output voltage
(VDD = 3.0 V)
0.4 V
IOH High-level source current, VOH = 2.4 6 mA
IOL Low-level sink current, VOH = 0.4 6 mA
Pin Internal Pullup and Pulldown (25°C)
IOH Pullup current, VOH = 2.4
(VDD = 3.0 V)
5 10 µA
IOL Pulldown current, VOL = 0.4
(VDD = 3.0 V)
5 µA
VIL nRESET(1) 0.6 V
(1) The nRESET pin must be held below 0.6 V for the module to register a reset.

4.7 Thermal Resistance Characteristics for MOB Package

JC Junction-to-case 9.08 0.00
JB Junction-to-board 10.34 0.00
JA Junction-to-free air 11.60 0.00
JMA Junction-to-moving air 5.05 < 1.00
PsiJT Junction-to-package top 9.08 0.00
PsiJB Junction-to-board 10.19 0.00
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:
  • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
  • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
(3) m/s = meters per second.

4.8 Reset Requirement

Operation mode level ViH 0.65 × VBAT V
Shutdown mode level(1) ViL 0 0.6 V V
Minimum time for nReset low for resetting the module 5 ms
Rise/fall times Tr/Tf 20 µs
(1) The nRESET pin must be held below 0.6 V for the module to register a reset.

4.9 Current Consumption

TA = +25°C, VBAT = 3.6 V

TX 1 DSSS TX power level = 0 272 mA
TX power level = 4 188
6 OFDM TX power level = 0 248
TX power level = 4 179
54 OFDM TX power level = 0 223
TX power level = 4 160
RX(2) 1 DSSS 53
54 OFDM 53
Idle connected(3) 0.715
LPDS 0.140
Hibernate 7 µA
Peak calibration current(2)(4) VBAT = 3.3 V 450 mA
VBAT = 2.3 V 620
(1) TX power level = 0 implies maximum power. TX power level = 4 implies output power backed off approximately 4 dB.
(2) The RX current is measured with a 1-Mbps throughput rate.
(3) DTIM = 1
(4) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. Calibration is performed sparingly, typically when coming out of Hibernate and only if temperature has changed by more than 20°C or the time elapsed from prior calibration is greater than 24 hours.
(5) The CC3100 system is a constant power-source system. The active current numbers scale inversely on the VBAT voltage supplied.
Note: The area enclosed in the circle represents a significant reduction in current when transitioning from TX power level 3 to 4. In the case of lower range requirements (13-dbm output power), TI recommends using TX power level 4 to reduce the current.
Figure 4-3 TX Power and IBAT vs TX Power Level Settings (1 DSSS)
scr_chart3_of_3_swas032.gifFigure 4-4 TX Power and IBAT vs TX Power Level Settings (6 OFDM)
scr_chart2_of_3_swas032.gifFigure 4-5 TX Power and IBAT vs TX Power Level Settings (54 OFDM)

4.10 WLAN RF Characteristics

WLAN Receiver Characteristics

TA = +25°C, VBAT = 2.3 to 3.6 V. Parameters measured at module pin on channel 7 (2442 MHz)
(8% PER for 11b rates, 10% PER for 11g/11n rates)(10% PER)(1)
1 DSSS –94.7 dBm
2 DSSS –92.6
11 CCK –87.0
6 OFDM –89.0
9 OFDM –88.0
18 OFDM –85.0
36 OFDM –79.5
54 OFDM –73.0
MCS7 (Mixed Mode) –69.0
Maximum input level
(10% PER)
802.11b –3.0
802.11g –9.0
(1) Sensitivity is 1-dB worse on channel 13 (2472 MHz).

4.10.1 WLAN Transmitter Characteristics(1)

TA = +25°C, VBAT = 2.3 to 3.6 V. Parameters measured at module pin on channel 7 (2442 MHz)
Max RMS Output Power measured at 1 dB
from IEEE spectral mask or EVM
1DSSS 17 dBm
2DSSS 17
11CCK 17.25
6OFDM 16.25
9OFDM 16.25
18OFDM 16
36OFDM 15
54OFDM 13.5
MCS7 (Mixed Mode) 12
Transmit center frequency accuracy –20 20 ppm
  1. Channel-to-channel variation is up to 2 dB. The edge channels (2412 and 2472 MHz) have reduced TX power to meet FCC emission limits.

4.11 Timing Characteristics

4.11.1 SPI Host Interface Timings

host_spi_int_tmg_swrs161.gifFigure 4-6 SPI Host Interface Timing(1)
F Clock frequency 20 MHz
TCLK Clock period 41.6 0.35 × VBAT ns
Duty cycle 45% 55%
Tis RX setup time: minimum time in which data is stable before capture edge 4 ns
Tih RX hold time: minimum time in which data is stable after capture edge 4 ns
Tod TX setup propagation time: maximum time from launch edge until data is stable 16 ns
Toh TX hold propagation time: minimum time of data stable after launch edge 24 ns
CL Capacitive load on interface 20 pF
(1) Ensure that nCS (active-low signal) is asserted 10 ns before the clock is toggled. nCS can be deasserted 10 ns after the clock edge

4.11.2 Wake-Up Sequence

td_startup_nRESET.gifFigure 4-7 Wake-Up Sequence

Table 4-1 First-Time Power-Up and Reset Removal Timing Requirements (32K XTAL)

T1 Supply settling time Depends on application board power supply, decap, and so on 3 ms
T2 Hardware wakeup time 25 ms
T3 Initialization time 32-kHz XTAL settling + firmware initialization time + radio calibration 1.35 s

4.11.3 Wakeup from Hibernate

Figure 4-8 shows the timing diagram for wakeup from the hibernate state.

td_hibernate.gifFigure 4-8 nHIB Timing Diagram


The internal 32.768-kHz crystal oscillator is kept enabled by default when the chip goes to hibernate in response to nHIB being pulled low.

Table 4-2 nHIB Timing Requirements(2)

Thib_min Minimum hibernate time Minimum LOW pulse width of nHIB 10 ms
Twake_from_hib Hardware wakeup time plus firmware initialization time See (1). 50 ms
(1) If temperature changes by more than 20°C, initialization time from HIB can increase by 200 ms due to radio calibration.
(2) Ensure that the nHIB low duration is not less than the specified width under all conditions, including power-ON, MCU hibernation, and so forth.

4.11.4 Interfaces

This section describes the interfaces that are supported by the CC3100 module:

  • Host SPI
  • Host UART Host SPI Interface Timing

SWAS032_017.gifFigure 4-9 Host SPI Interface Timing

Table 4-3 Host SPI Interface Timing Parameters

I1 F Clock frequency @ VBAT = 3.3 V 20 MHz
Clock frequency @ VBAT ≤ 2.1 V 12
I2 tclk(2) Clock period 50 ns
I3 tLP Clock low period 25 ns
I4 tHT Clock high period 25 ns
I5 D Duty cycle 45% 55%
I6 tIS RX data setup time 4 ns
I7 tIH RX data hold time 4 ns
I8 tOD TX data output delay 20
I9 tOH TX data hold time 24 ns
(1) The timing parameter has a maximum load of 20 pf at 3.3 V.
(2) Ensure that nCS (active-low signa)l is asserted 10 ns before the clock is toggled. nCS can be deasserted 10 ns after the clock edge. SPI Host Interface

The device interfaces to an external host using the SPI interface. The CC3100 device can interrupt the host using the HOST_INTR line to initiate the data transfer over the interface. The SPI host interface can work up to a speed of 20 MHz.

Figure 4-10 shows the SPI host interface.

SWAS031_027.gifFigure 4-10 SPI Host Interface

Table 4-4 lists the SPI host interface pins.

Table 4-4 SPI Host Interface

Pin Name Description
HOST_SPI_CLK Clock (up to 20 MHz) from MCU host to CC3100 device
HOST_SPI_nCS CS (active low) signal from MCU host to CC3100 device
HOST_SPI_MOSI Data from MCU host to CC3100 device
HOST_INTR Interrupt from CC3100 device to MCU host
HOST_SPI_MISO Data from CC3100 device to MCU host
nHIB Active-low signal that commands the CC3100 device to enter hibernate mode (lowest power state) Host UART

The SimpleLink device requires the UART configuration described in Table 4-5.

Table 4-5 SimpleLink UART Configuration

Property Supported CC3100 Configuration
Baud rate 115200 bps, no auto-baud rate detection, can be changed by the host up to 3 Mbps using a special command
Data bits 8 bits
Flow control CTS/RTS
Parity None
Stop bits 1
Bit order LSBit first
Host interrupt polarity Active high
Host interrupt mode Rising edge or level 1
Endianness Little-endian only(1)
(1) The SimpleLink device does not support automatic detection of the host length while using the UART interface. 5-Wire UART Topology

Figure 4-11 shows the typical 5-wire UART topology comprised of 4 standard UART lines plus one IRQ line from the device to the host controller to allow efficient low power mode.

SWAS031-088.gifFigure 4-11 Typical 5-Wire UART Topology

This is the typical and recommended UART topology because it offers the maximum communication reliability and flexibility between the host and the SimpleLink device. 4-Wire UART Topology

The 4-wire UART topology eliminates the host IRQ line (see Figure 4-12). Using this topology requires one of the following conditions to be met:

  • Host is always awake or active.
  • Host goes to sleep but the UART module has receiver start-edge detection for auto wakeup and does not lose data.
SWAS031-089.gifFigure 4-12 4-Wire UART Configuration 3-Wire UART Topology

The 3-wire UART topology requires only the following lines (see Figure 4-13):

  • RX
  • TX
  • CTS
SWAS031-090.gifFigure 4-13 3-Wire UART Topology

Using this topology requires one of the following conditions to be met:

  • Host always stays awake or active.
  • Host goes to sleep but the UART module has receiver start-edge detection for auto wakeup and does not lose data.
  • Host can always receive any amount of data transmitted by the SimpleLink device because there is no flow control in this direction.

Because there is no full flow control, the host cannot stop the SimpleLink device to send its data; thus, the following parameters must be carefully considered:

  • Max baud rate
  • RX character interrupt latency and low-level driver jitter buffer
  • Time consumed by the user's application