SWAS034 February   2017 CC3120

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Attributes
    3. 3.3 Connections for Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Power-On Hours
      1. 4.3.1 Recommended Operating Conditions
    4. 4.4  Current Consumption Summary
    5. 4.5  TX Power and IBAT versus TX Power Level Settings
    6. 4.6  Brownout and Blackout Conditions
    7. 4.7  Electrical Characteristics (3.3 V, 25°C)
    8. 4.8  WLAN Receiver Characteristics
    9. 4.9  WLAN Transmitter Characteristics
    10. 4.10 WLAN Filter Requirements
    11. 4.11 Thermal Resistance Characteristics for RGK Package
    12. 4.12 Timing and Switching Characteristics
      1. 4.12.1 Power Supply Sequencing
      2. 4.12.2 Device Reset
      3. 4.12.3 Reset Timing
        1. 4.12.3.1 nRESET (32k XTAL)
        2. 4.12.3.2 nRESET (External 32K)
        3. 4.12.3.3 Wakeup From HIBERNATE Mode
      4. 4.12.4 Clock Specifications
        1. 4.12.4.1 Slow Clock Using Internal Oscillator
        2. 4.12.4.2 Slow Clock Using an External Clock
        3. 4.12.4.3 Fast Clock (Fref) Using an External Crystal
        4. 4.12.4.4 Fast Clock (Fref) Using an External Oscillator
      5. 4.12.5 Interfaces
        1. 4.12.5.1 Host SPI Interface Timing
        2. 4.12.5.2 Flash SPI Interface Timing
    13. 4.13 External Interfaces
      1. 4.13.1 SPI Flash Interface
      2. 4.13.2 SPI Host Interface
    14. 4.14 Host UART
      1. 4.14.1 5-Wire UART Topology
      2. 4.14.2 4-Wire UART Topology
      3. 4.14.3 3-Wire UART Topology
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Device Features
      1. 5.3.1 WLAN
      2. 5.3.2 Network Stack
      3. 5.3.3 Security
      4. 5.3.4 Host Interface and Driver
      5. 5.3.5 System
    4. 5.4 Power-Management Subsystem
      1. 5.4.1 VBAT Wide-Voltage Connection
      2. 5.4.2 Preregulated 1.85V
    5. 5.5 Low-Power Operating Modes
      1. 5.5.1 Low-Power Deep Sleep
      2. 5.5.2 Hibernate
      3. 5.5.3 Shutdown
    6. 5.6 Memory
      1. 5.6.1 External Memory Requirements
    7. 5.7 Restoring Factory Default Configuration
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
      1. 6.1.1 Typical Application—CC3120R Wide-Voltage Mode
      2. 6.1.2 Typical Application Schematic—CC3120R Preregulated, 1.85-V Mode
    2. 6.2 PCB Layout Guidelines
      1. 6.2.1 General PCB Guidelines
      2. 6.2.2 Power Layout and Routing
        1. 6.2.2.1 Design Considerations
      3. 6.2.3 Clock Interfaces
      4. 6.2.4 Digital Input and Output
      5. 6.2.5 RF Interface
  7. 7Device and Documentation Support
    1. 7.1 Tools and Software
    2. 7.2 Device Nomenclature
    3. 7.3 Documentation Support
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGK|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Applications, Implementation, and Layout

NOTE

Information in the following Applications section is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Typical Application—CC3120R Wide-Voltage Mode

Figure 6-1 shows the typical application schematic using the CC3120R device in the wide-voltage mode of operation. For a full operation reference design, refer to the BoosterPack that uses the CC3120R device (see CC3120 SimpleLink™ and Internet of Things Hardware Design Files).

CC3120 CC3120V3V3_Final_figure_6.2.gif Figure 6-1 CC3120R Wide-Voltage Mode Application

Table 6-1 lists the bill of materials for an application using the CC3120R device in wide-voltage mode.

Table 6-1 Bill of Materials for CC3120R in Wide-Voltage Mode

QUANTITY PART REFERENCE VALUE MANUFACTURER PART NUMBER DESCRIPTION
1 C1 0.5 pF Murata GRM1555C1HR50BA01D CAP, CERM, 0.5 pF, 50 V, ±20%, C0G/NP0, 0402
2 C2, C3 100 µF Taiyo Yuden LMK325ABJ107MMHT CAP, CERM, 100 µF, 10 V, ±20%, X5R, AEC-Q200 Grade 3, 1210
3 C4, C5, C6 4.7 µF TDK C1005X5R0J475M050BC CAP, CERM, 4.7 µF, 6.3 V, ±20%, X5R, 0402
11 C7, C8, C9, C11, C13, C14, C15, C16, C18, C19, C27 0.1 µF TDK C1005X5R1A104K050BA CAP, CERM, 0.1 µF, 10 V, ±10%, X5R, 0402
3 C10, C17, C22 10 µF Murata GRM188R60J106ME47D CAP, CERM, 10 µF, 6.3 V, ±20%, X5R, 0603
1 C12 1 µF TDK C1005X5R1A105K050BB CAP, CERM, 1 µF, 10 V, ±10%, X5R, 0402
2 C20, C21 22 µF TDK C1608X5R0G226M080AA CAP, CERM, 22 µF, 4 V, ±20%, X5R, 0603
2 C23, C24 10 pF Johanson Technology 500R07S100JV4T CAP, CERM, 10 pF, 50 V, ±5%, C0G/NP0, 0402
2 C25, C26 6.2 pF Murata GRM1555C1H6R2CA01D CAP, CERM, 6.2 pF, 50 V, ±5%, C0G/NP0, 0402
1 E1 2.45-GHz Ant Taiyo Yuden AH316M245001-T ANT Bluetooth W-LAN ZIGBEE WIMAX, SMD
1 FL1 1.02 dB TDK DEA202450BT-1294C1-H Multilayer Chip Band Pass Filter For 2.4GHz W-LAN/Bluetooth, SMD
1 L1 3.3 nH Murata LQG15HS3N3S02D Inductor, Multilayer, Air Core, 3.3 nH, 0.3 A, 0.17 ohm, SMD
2 L2, L4 2.2 uH Murata LQM2HPN2R2MG0L Inductor, Multilayer, Ferrite, 2.2 µH, 1.3 A, 0.08 ohm, SMD
1 L3 1 uH Murata LQM2HPN1R0MG0L Inductor, Multilayer, Ferrite, 1 µH, 1.6 A, 0.055 ohm, SMD
1 R1 10 k Vishay-Dale CRCW040210K0JNED RES, 10 k, 5%, 0.063 W, 0402
1 R11 2.7 k Vishay-Dale CRCW04022K70JNED RES, 2.7 k, 5%, 0.063 W, 0402
10 R2, R3, R4, R5, R6, R7, R9, R10, R12, R13 100 k Vishay-Dale CRCW0402100KJNED RES, 100 k, 5%, 0.063 W, 0402
1 U1 MX25R Macronix International MX25R1635FM1IL0 ULTRA LOW POWER, 16M-BIT [x 1/x 2/x 4] CMOS MXSMIO(SERIAL MULTI I/O) FLASH MEMORY, SOP-8
1 U2 CC3120 Texas Instruments CC3120RNMRGK SimpleLink Wi-Fi Network Processor, Internet-of-Things Solution for MCU Applications, RGK0064B
1 Y1 Crystal Abracon Corporation ABS07-32.768KHZ-9-T CRYSTAL, 32.768KHZ, 9PF, SMD
1 Y2 Crystal Epson Q24FA20H0039600 Crystal, 40MHz, 8pF, SMD

Typical Application Schematic—CC3120R Preregulated, 1.85-V Mode

Figure 6-2 shows the typical application schematic using the CC3120R in preregulated, 1.85-V mode of operation. For addition information on this mode of operation please contact your TI representative.

CC3120 CC3120R_preregulated_voltage_schematic.gif Figure 6-2 CC3120R Preregulated 1.85-V Mode Application Circuit

Table 6-2 lists the bill of materials for an application using the CC3120R device in preregulated 1.85-V mode.

Table 6-2 Bill of Materials for CC3120R in Preregulated, 1.85-V Mode

QUANTITY DESIGNATOR VALUE MANUFACTURER PART NUMBER DESCRIPTION
1 U1 MX25R Macronix International Co., LTD MX25R1635FM1IL0 ULTRA LOW POWER, 16M-BIT [x 1/x 2/x 4] CMOS MXSMIO(SERIAL MULTI I/O) FLASH MEMORY, SOP-8
1 U2 CC3120 Texas Instruments CC3120RNMRGK SimpleLink Wi-Fi Network Processor, Internet-of-Things Solution for MCU Applications, RGK0064B
1 R10 2.7 k Vishay-Dale CRCW04022K70JNED RES, 2.7 k, 5%, 0.063 W, 0402
10 R2, R3, R4, R5, R6, R7, R8, R9, R11, R12 100 k Vishay-Dale CRCW0402100KJNED RES, 100 k, 5%, 0.063 W, 0402
1 R1 10 k Vishay-Dale CRCW040210K0JNED RES, 10 k, 5%, 0.063 W, 0402
1 FL1 1.02 dB TDK DEA202450BT-1294C1-H Multilayer Chip Band Pass Filter For 2.4-GHz W-LAN/Bluetooth, SMD
1 L2 2.2 µH MuRata LQM2HPN2R2MG0L Inductor, Multilayer, Ferrite, 2.2 µH, 1.3 A, 0.08 ohm, SMD
1 L1 3.3 nH MuRata LQG15HS3N3S02D Inductor, Multilayer, Air Core, 3.3 nH, 0.3 A, 0.17 Ω, SMD
1 Y1 Crystal Abracon Corportation ABS07-32.768KHZ-9-T CRYSTAL, 32.768 kHz, 9 pF, SMD
1 Y2 Crystal Epson Q24FA20H0039600 Crystal, 40 MHz, 8 pF, SMD
2 C2, C3 100 µF Taiyo Yuden LMK325ABJ107MMHT CAP, CERM, 100 µF, 10 V, ±20%, X5R, AEC-Q200 Grade 3, 1210
1 C13 22 µF TDK C1608X5R0G226M080AA CAP, CERM, 22 µF, 4 V, ±20%, X5R, 0603
2 C10, C20 10 µF MuRata GRM188R60J106ME47D CAP, CERM, 10 µF, 6.3 V, ±20%, X5R, 0603
2 C21, C22 10 pF Johanson Technology 500R07S100JV4T CAP, CERM, 10 pF, 50 V, ±5%, C0G/NP0, 0402
2 C23, C24 6.2 pF MuRata GRM1555C1H6R2CA01D CAP, CERM, 6.2 pF, 50 V, ±5%, C0G/NP0, 0402
3 C4, C5, C6 4.7 µF TDK C1005X5R0J475M050BC CAP, CERM, 4.7 µF, 6.3 V, ±20%, X5R, 0402
1 C12 1 µF TDK C1005X5R1A105K050BB CAP, CERM, 1 µF, 10 V, ±10%, X5R, 0402
1 C1 0.5 pF MuRata GRM1555C1HR50BA01D CAP, CERM, 0.5 pF, 50 V, ±20%, C0G/NP0, 0402
11 C7, C8, C9, C11, C14, C15, C16, C17, C18, C19, C25 0.1 µF TDK C1005X5R1A104K050BA CAP, CERM, 0.1 µF, 10 V, ±10%, X5R, 0402
1 E1 2.45-Ghz Ant Taiyo Yuden AH316M245001-T ANT BLUETOOTH W-LAN ZIGBEE WIMAX, SMD

PCB Layout Guidelines

This section details the PCB guidelines to speed up the PCB design using the CC3120R VQFN device. Follow these guidelines ensures that the design will minimize the risk with regulatory certifications including FCC, ETSI, and CE. For more information, see CC3120 and CC3220 SimpleLink™ Wi-Fi® and IoT Solution Layout Guidelines.

General PCB Guidelines

Use the following PCB guidelines:

  • Verify the recommended PCB stackup in the PCB design guidelines, as well as the recommended layers for signals and ground.
  • Ensure that the QFN PCB footprint follows the information in Section 8.
  • Ensure that the QFN PCB GND and solder paste follow the recommendations provided in CC3120 and CC3220 SimpleLink™ Wi-Fi® and IoT Solution Layout Guidelines.
  • Decoupling capacitors must be as close as possible to the QFN device.

Power Layout and Routing

Three critical DC-DC converters must be considered for the CC3120R device.

  • Analog DC-DC converter
  • PA DC-DC converter
  • Digital DC-DC converter

Each converter requires an external inductor and capacitor that must be laid out with care. DC current loops are formed when laying out the power components.

Design Considerations

The following design guidelines must be followed when laying out the CC3120R device:

  • Route all of the input decoupling capacitors (C11, C13, and C18) on L2 using thick traces, to isolate the RF ground from the noisy supply ground. This step is also required to meet the IEEE spectral mask specifications.
  • Maintain the thickness of power traces to be greater than 12 mils. Take special consideration for power amplifier supply lines (pin 33, 40, 41, and 42), and all input supply pins (pin 37, 39, and 44).
  • Ensure the shortest grounding loop for the PLL supply decoupling capacitor (pin 24).
  • Place all decoupling capacitors as close to the respective pins as possible.
  • Power budget: The CC3120R device can consume up to 450 mA for 3.3 V, 670 mA for 2.1 V, and 700 mA for 1.85 V, for 24 ms during the calibration cycle.
  • Ensure the power supply is designed to source this current without any issues. The complete calibration (TX and RX) can take up to 17 mJ of energy from the battery over a time of 24 ms.
  • The CC3120R device contains many high-current input pins. Ensure the trace feeding these pins is capable of handling the following currents:
    • PA DCDC input (pin 39) maximum 1 A
    • ANA DCDC input (pin 37) maximum 600 mA
    • DIG DCDC input (pin 44) maximum 500 mA
    • PA DCDC switching nodes (pin 40 and pin 41) maximum 1 A
    • PA DCDC output node (pin 42) maximum 1 A
    • ANA DCDC switching node (pin 38) maximum 600 mA
    • DIG DCDC switching node (pin 43) maximum 500 mA
    • PA supply (pin 33) maximum 500 mA

Figure 6-3 shows the ground routing for the input decoupling capacitors.

CC3120 ground_routing_input.png Figure 6-3 Ground Routing for the Input Decoupling Capacitors

The ground return for the input capacitors are routed on L2 to reduce the EMI and improve the spectral mask. This routing must be strictly followed because it is critical for the overall performance of the device.

Clock Interfaces

The following guidelines are for the slow clock.

  • The 32.768-kHz crystal must be placed close to the QFN package.
  • Ensure that the load capacitance is tuned according to the board parasitics to the frequency tolerance is within ±150 ppm.
  • The ground plane on layer two is solid below the trace lanes and there is ground around these traces on the top layer.

The following guidelines are for the fast clock.

  • The 40-MHz crystal must be placed close to the QFN package.
  • Ensure that he load capacitance is tuned according to the board parasitics to the frequency tolerance is within ±100 ppm at room temperature. The total frequency across parts, temperature, and with aging, must be ±25 ppm to meet the WLAN specification.
  • Ensure that no high-frequency lines are routed close to the XTAL routing to avoid noise degradation.
  • Ensure that crystal tuning capacitors are close to the crystal pads.
  • Make both traces (XTALM and XTALP) as close to parallel as possible and approximately the same length.
  • The ground plane on layer two is solid below the trace lines and that there is ground around these traces on the top layer.
  • See CC31xx & CC32xx Frequency Tuning for frequency tuning.

Digital Input and Output

The following guidelines are for the digital I/O.

  • Route SPI and UART lines away from any RF traces.
  • Keep the length of the high-speed lines as short as possible to avoid transmission line effects.
  • Keep the line lower than 1/10 of the rise time of the signal to ignore transmission line effects. This is required if the traces cannot be kept short. Place the resistor at the source end, closer to the device that is driving the signal.
  • Add series-terminating resistor for each high-speed line (such as SPI_CLK or SPI_DATA) to match the driver impedance to the line. Typical terminating-resistor values range from 27 to 36 Ω for a 50-Ω line impedance.
  • Route high-speed lines with a ground reference plane continuously below it to offer good impedance throughout. This routing also helps shield the trace against EMI.
  • Avoid stubs on high-speed lines to minimize the reflections. If the line must be routed to multiple locations, use a separate line driver for each line.
  • If the lines are longer compared to the rise time, add series-terminating resistors near the driver for each high-speed line to match the driver impedance to the line. Typical terminating-resistor values range from 27 to 36 Ω for a 50-Ω line impedance.

RF Interface

The following guidelines are for the RF interface. Follow guidelines specified in the vendor-specific antenna design guides (including placement of the antenna). Also see CC3120 and CC3220 SimpleLink™ Wi-Fi® and IoT Solution Layout Guidelines for general antenna guidelines.

  • Ensure that the antenna is matched for 50-Ω. A Pi-matching network is recommended.
  • Ensure that the area underneath the BPF pads are grounded on layer one and layer two, and that the minimum fulter requirements are met.
  • Verify that the Wi-Fi RF trace is a 50-Ω, impedance-controlled trace with a reference to solid ground.
  • The RF trace bends must be made with gradual curves, and 90-degree bends must be avoided.
  • The RF traces must not have sharp corners.
  • There must be no traces or ground under the antenna section.
  • The RF traces must have via stitching on the ground plane beside the RF trace on both sides.