SWAS034 February   2017 CC3120

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Attributes
    3. 3.3 Connections for Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Power-On Hours
      1. 4.3.1 Recommended Operating Conditions
    4. 4.4  Current Consumption Summary
    5. 4.5  TX Power and IBAT versus TX Power Level Settings
    6. 4.6  Brownout and Blackout Conditions
    7. 4.7  Electrical Characteristics (3.3 V, 25°C)
    8. 4.8  WLAN Receiver Characteristics
    9. 4.9  WLAN Transmitter Characteristics
    10. 4.10 WLAN Filter Requirements
    11. 4.11 Thermal Resistance Characteristics for RGK Package
    12. 4.12 Timing and Switching Characteristics
      1. 4.12.1 Power Supply Sequencing
      2. 4.12.2 Device Reset
      3. 4.12.3 Reset Timing
        1. 4.12.3.1 nRESET (32k XTAL)
        2. 4.12.3.2 nRESET (External 32K)
        3. 4.12.3.3 Wakeup From HIBERNATE Mode
      4. 4.12.4 Clock Specifications
        1. 4.12.4.1 Slow Clock Using Internal Oscillator
        2. 4.12.4.2 Slow Clock Using an External Clock
        3. 4.12.4.3 Fast Clock (Fref) Using an External Crystal
        4. 4.12.4.4 Fast Clock (Fref) Using an External Oscillator
      5. 4.12.5 Interfaces
        1. 4.12.5.1 Host SPI Interface Timing
        2. 4.12.5.2 Flash SPI Interface Timing
    13. 4.13 External Interfaces
      1. 4.13.1 SPI Flash Interface
      2. 4.13.2 SPI Host Interface
    14. 4.14 Host UART
      1. 4.14.1 5-Wire UART Topology
      2. 4.14.2 4-Wire UART Topology
      3. 4.14.3 3-Wire UART Topology
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Device Features
      1. 5.3.1 WLAN
      2. 5.3.2 Network Stack
      3. 5.3.3 Security
      4. 5.3.4 Host Interface and Driver
      5. 5.3.5 System
    4. 5.4 Power-Management Subsystem
      1. 5.4.1 VBAT Wide-Voltage Connection
      2. 5.4.2 Preregulated 1.85V
    5. 5.5 Low-Power Operating Modes
      1. 5.5.1 Low-Power Deep Sleep
      2. 5.5.2 Hibernate
      3. 5.5.3 Shutdown
    6. 5.6 Memory
      1. 5.6.1 External Memory Requirements
    7. 5.7 Restoring Factory Default Configuration
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
      1. 6.1.1 Typical Application—CC3120R Wide-Voltage Mode
      2. 6.1.2 Typical Application Schematic—CC3120R Preregulated, 1.85-V Mode
    2. 6.2 PCB Layout Guidelines
      1. 6.2.1 General PCB Guidelines
      2. 6.2.2 Power Layout and Routing
        1. 6.2.2.1 Design Considerations
      3. 6.2.3 Clock Interfaces
      4. 6.2.4 Digital Input and Output
      5. 6.2.5 RF Interface
  7. 7Device and Documentation Support
    1. 7.1 Tools and Software
    2. 7.2 Device Nomenclature
    3. 7.3 Documentation Support
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGK|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over process and voltage, unless otherwise indicated.

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VBAT and VIO Pins: 37, 39, 44 –0.5 3.8 V
VIO – VBAT (differential) Pins: 10, 54 0.0 V
Digital inputs –0.5 VIO + 0.5 V
RF pins –0.5 2.1 V
Analog pins, XTAL Pins: 22, 23, 51, 52 –0.5 2.1 V
Operating temperature, TA –40 85 °C
Storage temperature, Tstg –55 125 °C

ESD Ratings

VALUE UNIT
VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Power-On Hours

NOTE

This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products.

CONDITIONS POH
TA up to 85°C(1) 87,600
The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the remaining 90% of the time, the device can be in any other state.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN TYP MAX UNIT
VBAT, VIO
(shorted to VBAT)
Pins: 10, 37, 39, 44, 54 Direct battery connection(3) 2.1(6) 3.3 3.6 V
Preregulated 1.85 V(4)(5)
Ambient thermal slew –20 20 °C/minute
Operating temperature is limited by crystal frequency variation.
When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the transmission.
To ensure WLAN performance, ripple on the 2.1- to 3.3-V supply must be less than ±300 mV.
To ensure WLAN performance, ripple on the 1.85-V supply must be less than 2% (±40 mV).
TI recommends keeping VBAT above 1.85 V. For lower voltages, use a boost converter.
The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also 2.1 V, and care must be taken when operating at the minimum specified voltage.

Current Consumption Summary

TA = 25°C, VBAT = 3.6 V
PARAMETER TEST CONDITIONS(1)(4) MIN TYP MAX UNIT
TX 1 DSSS TX power level = 0 272 mA
TX power level = 4 188
6 OFDM TX power level = 0 248
TX power level = 4 179
54 OFDM TX power level = 0 223
TX power level = 4 160
RX(6) 1 DSSS 53 mA
54 OFDM 53
Idle connected(2) 690 µA
LPDS 115
Hibernate(5) 4
Peak calibration current(3)(6) VBAT = 3.3 V 450 mA
VBAT = 2.1 V 670
VBAT = 1.85 V 700
TX power level = 0 implies maximum power (see Figure 4-1, Figure 4-2, and Figure 4-3). TX power level = 4 implies output power backed off approximately 4 dB.
DTIM = 1
The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C. There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further details, see CC3120, CC3220 SimpleLink™ Wi-F and IoT Network Processor Programmer's Guide.
The CC3120R system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
For the 1.85-V mode, the hibernate current is higher by 50 µA across all operating modes because of leakage into the PA and analog power inputs.
The RX current is measured with a 1-Mbps throughput rate.

TX Power and IBAT versus TX Power Level Settings

Figure 4-1, Figure 4-2, and Figure 4-3 show TX Power and IBAT versus TX power level settings for modulations of 1 DSSS, 6 OFDM, and 54 OFDM, respectively.

In Figure 4-1, the area enclosed in the circle represents a significant reduction in current during transition from TX power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI recommends using TX power level 4 to reduce the current.

CC3120 scr_chart1_of_3_swas032.gif Figure 4-1 TX Power and IBAT vs TX Power Level Settings (1 DSSS)
CC3120 scr_chart3_of_3_swas032.gif Figure 4-2 TX Power and IBAT vs TX Power Level Settings (6 OFDM)
CC3120 scr_chart2_of_3_swas032.gif Figure 4-3 TX Power and IBAT vs TX Power Level Settings (54 OFDM)

Brownout and Blackout Conditions

The device enters a brownout condition when the input voltage drops below Vbrownout (see Figure 4-4 and Figure 4-5). This condition must be considered during design of the power supply routing, especially when operating from a battery. High-current operations, such as a TX packet or any external activity (not necessarily related directly to networking) can cause a drop in the supply voltage, potentially triggering a brownout condition. The resistance includes the internal resistance of the battery, the contact resistance of the battery holder (four contacts for 2× AA batteries), and the wiring and PCB routing resistance.

NOTE

When the device is in HIBERNATE state, brownout is not detected. Only blackout is in effect during HIBERNATE state.

CC3120 Black_Brownout_Levels1_swas031.gif Figure 4-4 Brownout and Blackout Levels (1 of 2)
CC3120 Black_Brownout_Levels2_swas031.gif Figure 4-5 Brownout and Blackout Levels (2 of 2)

In the brownout condition, all sections of the device (including the 32-kHz RTC) shut down except for the Hibernate module, which remains on. The current in this state can reach approximately 400 µA. The blackout condition is equivalent to a hardware reset event in which all states within the device are lost.

Table 4-1 lists the brownout and blackout voltage levels.

Table 4-1 Brownout and Blackout Voltage Levels

CONDITION VOLTAGE LEVEL UNIT
Vbrownout 2.1 V
Vblackout 1.67 V

Electrical Characteristics (3.3 V, 25°C)

GPIO Pins Except 29, 30, 50, 52, and 53 (25°C)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
CIN Pin capacitance 4 pF
VIH High-level input voltage 0.65 × VDD VDD + 0.5 V V
VIL Low-level input voltage –0.5 0.35 × VDD V
IIH High-level input current 5 nA
IIL Low-level input current 5 nA
VOH High-level output voltage
IL = 2 mA; configured I/O drive strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.8 V
IL = 4 mA; configured I/O drive strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 8 mA; configured I/O drive strength = 8 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 2 mA; configured I/O drive strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.75
IL = 2 mA; configured I/O drive strength = 2 mA;
VDD = 1.85 V
VDD × 0.7
VOL Low-level output voltage
IL = 2 mA; configured I/O drive strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2 V
IL = 4 mA; configured I/O drive strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 8 mA; configured I/O drive strength = 8 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 2 mA; configured I/O drive strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.25
IL = 2 mA; configured I/O drive strength = 2 mA;
VDD = 1.85 V
VDD × 0.35
IOH High-level source current,
2-mA drive 2 mA
4-mA drive 4
6-mA drive 6
IOL Low-level sink current,
2-mA drive 2 mA
4-mA drive 4
6-mA drive 6
VIL nRESET(1) 0.6 V
The nRESET pin must be held below 0.6 V for the device to register a reset.

WLAN Receiver Characteristics

TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters are measured at the SoC pin on channel 6 (2437 MHz).
PARAMETER TEST CONDITIONS (Mbps) MIN TYP(1) MAX UNIT
Sensitivity
(8% PER for 11b rates, 10% PER for 11g/11n rates) (10% PER)(3)
1 DSSS 96.0 dBm
2 DSSS 94.0
11 CCK 88.0
6 OFDM 90.5
9 OFDM 90.0
18 OFDM 86.5
36 OFDM 80.5
54 OFDM 74.5
MCS7 (GF)(2) 71.5
MCS7 (MM)(2) 70.5
Maximum input level
(10% PER)
802.11b –4.0 dBm
802.11g –10.0
In preregulated 1.85-V mode, RX sensitivity is 0.25- to 1-dB lower.
Sensitivity for mixed mode is 1-dB worse.
Sensitivity is 1-dB worse on channel 13 (2472 MHz).

WLAN Transmitter Characteristics

TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters measured at SoC pin on channel 7 (2442 MHz).(1)
PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT
Maximum RMS output power measured at 1 dB from IEEE spectral mask or EVM 1 DSSS +18.0 dBm
2 DSSS +18.0
11 CCK +18.3
6 OFDM +17.3
9 OFDM +17.3
18 OFDM +17.0
36 OFDM +16.0
54 OFDM +14.5
MCS7 (MM) +13.0
Transmit center frequency accuracy –25 25 ppm
Channel-to-channel variation is up to 2 dB. The edge channels (2412 and 2472 MHz) have reduced TX power to meet FCC emission limits.
In preregulated 1.85-V mode, maximum TX power is 0.25- to 0.75-dB lower for modulations higher than 18 OFDM.

WLAN Filter Requirements

The device requires an external band-pass filter to meet the various emission standards, including FCC. Table 4-2 presents the attenuation requirements for the band-pass filter. TI recommends using the same filter used in the reference design to ease the process of certification.

Table 4-2 WLAN Filter Requirements

PARAMETER FREQUENCY (MHz) MIN TYP MAX UNIT
Return loss 2412 to 2484 10 dB
Insertion loss(1) 2412 to 2484 1 1.5 dB
Attenuation 800 to 830 30 45 dB
1600 to 1670 20 25
3200 to 3300 30 48
4000 to 4150 45 50
4800 to 5000 20 25
5600 to 5800 20 25
6400 to 6600 20 35
7200 to 7500 35 45
7500 to 10000 20 25
Reference impendence 2412 to 2484 50 Ω
Filter type Bandpass
Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation requirements.

Thermal Resistance Characteristics for RGK Package

AIR FLOW
PARAMETER 0 lfm (C/W) 150 lfm (C/W) 250 lfm (C/W) 500 lfm (C/W)
θja 23 14.6 12.4 10.8
Ψjt 0.2 0.2 0.3 0.1
Ψjb 2.3 2.3 2.2 2.4
θjc 6.3
θjb 2.4

Timing and Switching Characteristics

Power Supply Sequencing

For proper operation of the CC3120R device, perform the recommended power-up sequencing as follows:

  1. Tie VBAT (pins 37, 39, 44) and VIO (pins 54 and 10) together on the board.
  2. Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit (100 K ||, 1 µF, RC = 100 ms).
  3. For an external RTC, ensure that the clock is stable before RESET is deasserted (high).

For timing diagrams, see Section 4.12.3.

Device Reset

When a device restart is required, the user may either issue a negative pulse on the nHIB pin (pin 2) or on the nRESET pin (pin 32), keeping the other pulled high, depending on the configuration of the platform. In case the nRESET pin is used, the user must follow one of the two alternatives to ensure the reset is properly applied:

  • A high-to-low reset pulse (on pin 32) of at least 200-mS duration
  • If the above cannot be ensured, a pulldown resistor of 2M Ω should be connected to pin 32 (RTC_XTAL_N). If implemented, a shorter pulse of at least 100 uSec can be used.

To ensure a proper reset sequence, the user has to call the sl_stop function prior to toggling the reset.

Reset Timing

nRESET (32k XTAL)

Figure 4-6 shows the reset timing diagram for the 32k XTAL first-time power-up and reset removal.

CC3120 CC3100_Power_Up_Xtal.gif Figure 4-6 First-Time Power-Up and Reset Removal Timing Diagram (32k XTAL)

Table 4-3 describes the timing requirements for the XTAL first-time power-up and reset removal.

Table 4-3 First-Time Power-Up and Reset Removal Timing Requirements (32k XTAL)

ITEM NAME DESCRIPTION MIN TYP MAX UNIT
T1 Supply settling time Depends on application board power supply, decoupling capacitor, and so on 3 ms
T2 Hardware wake-up time 25 ms
T3 Initialization time 32-kHz XTAL settling plus firmware initialization time plus radio calibration 1.35 s

nRESET (External 32K)

Figure 4-7 shows the reset timing diagram for the external 32K first-time power-up and reset removal.

CC3120 CC3100_Power_Up_Ext_32K.gif Figure 4-7 First-Time Power-Up and Reset Removal Timing Diagram (External 32K)

describes the timing requirements for the external first-time power-up and reset removal.

Table 4-4 First-Time Power-Up and Reset Removal Timing Requirements (External 32K)

ITEM NAME DESCRIPTION MIN TYP MAX UNIT
T1 Supply settling time Depends on application board power supply, decoupling capacitor, and so on 3 ms
T2 Hardware wake-up time 25 ms
T3 Initialization time Firmware initialization time plus radio calibration 250 ms

Wakeup From HIBERNATE Mode

Figure 4-8 shows the timing diagram for wakeup from HIBERNATE mode.

CC3120 3100_nHIB.gif Figure 4-8 nHIB Timing Diagram

NOTE

The 32.768-kHz XTAL is kept enabled by default when the chip goes into HIBERNATE mode in response to nHIB being pulled low.

Table 4-5 describes the timing requirements for nHIB.

Table 4-5 nHIB Timing Requirements

ITEM NAME DESCRIPTION MIN TYP MAX UNIT
Thib_min Minimum hibernate time Minimum pulse width of nHIB being low(2) 10 ms
Twake_from_hib Hardware wakeup time plus firmware initialization time See(1) 50 ms
If temperature changes by more than 20°C, initialization time from HIB can increase by 200 ms due to radio calibration.
Ensure that the nHIB pulse width is kept above the minimum requirement under all conditions (such as power up, MCU reset, and so on).

Clock Specifications

The CC3120R device requires two separate clocks for its operation:

  • A slow clock running at 32.768 kHz is used for the RTC.
  • A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN subsystem.

The device features internal oscillators that enable the use of less-expensive crystals rather than dedicated TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system and to reduce overall cost.

Slow Clock Using Internal Oscillator

The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P (pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance to meet the ppm requirement.

Figure 4-9 shows the crystal connections for the slow clock.

CC3120 CC31x0_RTC_XTAL.gif Figure 4-9 RTC Crystal Connections

Table 4-6 lists the RTC crystal requirements.

Table 4-6 RTC Crystal Requirements

CHARACTERISTICS TEST CONDITIONS MIN TYP MAX UNIT
Frequency 32.768 kHz
Frequency accuracy Initial plus temperature plus aging ±150 ppm
Crystal ESR 32.768 kHz 70

Slow Clock Using an External Clock

When an RTC oscillator is present in the system, the CC3120R device can accept this clock directly as an input. The clock is fed on the RTC_XTAL_P line, and the RTC_XTAL_N line is held to VIO. The clock must be a CMOS-level clock compatible with VIO fed to the device.

Figure 4-10 shows the external RTC input connection.

CC3120 CC31x0_Ext_RTC_ClkIn.gif Figure 4-10 External RTC Input

Table 4-7 lists the external RTC digital clock requirements.

Table 4-7 External RTC Digital Clock Requirements

CHARACTERISTICS TEST CONDITIONS MIN TYP MAX UNIT
Frequency 32768 Hz
Frequency accuracy
(Initial plus temperature plus aging)
±150 ppm
tr, tf Input transition time tr, tf (10% to 90%) 100 ns
Frequency input duty cycle 20% 50% 80%
Vih Slow clock input voltage limits Square wave, DC coupled 0.65 × VIO VIO V
Vil 0 0.35 × VIO Vpeak
Input impedance 1
5 pF

Fast Clock (Fref) Using an External Crystal

The CC3120R device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The XTAL is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading capacitors.

Figure 4-11 shows the crystal connections for the fast clock.

CC3120 CC31x0_Fast_Clk_XTAL.gif

NOTE:

The XTAL capacitance must be tuned to ensure that the PPM requirement is met. See CC31xx & CC32xx Frequency Tuning for information on frequency tuning.
Figure 4-11 Fast Clock Crystal Connections

Table 4-8 lists the WLAN fast-clock crystal requirements.

Table 4-8 WLAN Fast-Clock Crystal Requirements

CHARACTERISTICS TEST CONDITIONS MIN TYP MAX UNIT
Frequency 40 MHz
Frequency accuracy Initial plus temperature plus aging ±25 ppm
Crystal ESR 40 MHz 60 Ω

Fast Clock (Fref) Using an External Oscillator

The CC3120R device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the system.

If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the LDO improves noise on the TCXO power supply.

Figure 4-12 shows the connection.

CC3120 CC3120_Ex_TCXO_In.gif Figure 4-12 External TCXO Input

Table 4-9 lists the external Fref clock requirements.

Table 4-9 External Fref Clock Requirements (–40°C to +85°C)

CHARACTERISTICS TEST CONDITIONS MIN TYP MAX UNIT
Frequency 40.00 MHz
Frequency accuracy (Initial plus temperature plus aging) ±25 ppm
Frequency input duty cycle 45% 50% 55%
Vpp Clock voltage limits Sine or clipped sine wave, AC coupled 0.7 1.2 Vpp
Phase noise @ 40 MHz @ 1 kHz –125 dBc/Hz
@ 10 kHz –138.5
@ 100 kHz –143
Input impedance Resistance 12
Capacitance 7 pF

Interfaces

This section describes the interfaces that are supported by the CC3120R device:

  • Host SPI
  • Flash SPI

Host SPI Interface Timing

Figure 4-13 shows the Host SPI interface timing diagram.

CC3120 SWAS032_017.gif Figure 4-13 Host SPI Interface Timing

Table 4-10 lists the Host SPI interface timing parameters.

Table 4-10 Host SPI Interface Timing Parameters

PARAMETER
NUMBER
MIN MAX UNIT
I1 F(1) Clock frequency @ VBAT = 3.3 V 20 MHz
Clock frequency @ VBAT ≤ 2.1 V 12
I2 tclk(2)(1) Clock period 50 ns
I3 tLP(1) Clock low period 25 ns
I4 tHT(1) Clock high period 25 ns
I5 D(1) Duty cycle 45% 55%
I6 tIS(1) RX data setup time 4 ns
I7 tIH(1) RX data hold time 4 ns
I8 tOD(1) TX data output delay 20 ns
I9 tOH(1) TX data hold time 24 ns
The timing parameter has a maximum load of 20 pF at 3.3 V.
Ensure that nCS (active-low signal) is asserted 10 ns before the clock is toggled. nCS can be deasserted 10 ns after the clock edge.

Flash SPI Interface Timing

Figure 4-14 shows the Flash SPI interface timing diagram.

CC3120 SWAS032_017.gif Figure 4-14 Flash SPI Interface Timing

Table 4-11 lists the Flash SPI interface timing parameters.

Table 4-11 Flash SPI Interface Timing Parameters

PARAMETER
NUMBER
MIN MAX UNIT
I1 F Clock frequency 20 MHz
I2 tclk Clock period 50 ns
I3 tLP Clock low period 25 ns
I4 tHT Clock high period 25 ns
I5 D Duty cycle 45% 55%
I6 tIS RX data setup time 1 ns
I7 tIH RX data hold time 2 ns
I8 tOD TX data output delay 8.5 ns
I9 tOH TX data hold time 8 ns

External Interfaces

SPI Flash Interface

The external serial flash stores the user profiles and firmware patch updates. The CC3120R device acts as a master in this case; the SPI serial flash acts as the slave device. This interface can work up to a speed of 20 MHz.

Figure 4-15 shows the SPI flash interface.

CC3120 CC3120_SPI_Flash_Int.gif Figure 4-15 SPI Flash Interface

Table 4-12 lists the SPI flash interface pins.

Table 4-12 SPI Flash Interface

PIN NAME DESCRIPTION
FLASH_SPI_CLK Clock (up to 20 MHz) CC3120R device to serial flash
FLASH_SPI_CS CS signal from CC3120R device to serial flash
FLASH_SPI_MISO Data from serial flash to CC3120R device
FLASH_SPI_MOSI Data from CC3120R device to serial flash

SPI Host Interface

The device interfaces to an external host using the SPI interface. The CC3120R device can interrupt the host using the HOST_INTR line to initiate the data transfer over the interface. The SPI host interface can work up to a speed of 20 MHz.

Figure 4-16 shows the SPI host interface.

CC3120 CC3120_SPI_Host_Int.gif Figure 4-16 SPI Host Interface

Table 4-13 lists the SPI host interface pins.

Table 4-13 SPI Host Interface

PIN NAME DESCRIPTION
HOST_SPI_CLK Clock (up to 20 MHz) from MCU host to CC3120R device
HOST_SPI_nCS CS (active low) signal from MCU host to CC3120R device
HOST_SPI_MOSI Data from MCU host to CC3120R device
HOST_INTR Interrupt from CC3120R device to MCU host
HOST_SPI_MISO Data from CC3120R device to MCU host
nHIB Active-low signal that commands the CC3120R device to enter hibernate mode (lowest power state)

Host UART

The SimpleLink device requires the UART configuration described in Table 4-14.

Table 4-14 SimpleLink UART Configuration

PROPERTY SUPPORTED CC3120R CONFIGURATION
Baud rate 115200 bps, no auto-baud rate detection, can be changed by the host up to 3 Mbps using a special command
Data bits 8 bits
Flow control CTS/RTS
Parity None
Stop bits 1
Bit order LSBit first
Host interrupt polarity Active high
Host interrupt mode Rising edge or level 1
Endianness Little-endian only(1)
The SimpleLink device does not support automatic detection of the host length while using the UART interface.

5-Wire UART Topology

Figure 4-17 shows the typical 5-wire UART topology comprised of four standard UART lines plus one IRQ line from the device to the host controller to allow efficient low-power mode.

CC3120 CC3120_5_Wire_UART.gif Figure 4-17 Typical 5-Wire UART Topology

This topology is recommended because the configuration offers the maximum communication reliability and flexibility between the host and the SimpleLink device.

4-Wire UART Topology

The 4-wire UART topology eliminates the host IRQ line (see Figure 4-18). Using this topology requires meeting one of the following conditions:

  • The host is always awake or active.
  • The host goes to sleep, but the UART module has receiver start-edge detection for auto wakeup and does not lose data.
CC3120 CC3120_4_Wire_UART.gif Figure 4-18 4-Wire UART Configuration

3-Wire UART Topology

The 3-wire UART topology requires only the following lines (see Figure 4-19):

  • RX
  • TX
  • CTS
CC3120 CC3120_3_Wire_UART.gif Figure 4-19 3-Wire UART Topology

Using this topology requires meeting one of the following conditions:

  • The host always stays awake or active.
  • The host goes to sleep but the UART module has receiver start-edge detection for auto-wake-up and does not lose data.
  • The host can always receive any amount of data transmitted by the SimpleLink device because there is no flow control in this direction.

Because there is no full flow control, the host cannot stop the SimpleLink device to send its data; thus, the following parameters must be carefully considered:

  • Maximum baud rate
  • RX character interrupt latency and low-level driver jitter buffer
  • Time consumed by the user's application