SWRS206C March   2017  – December 2018 CC3220MOD , CC3220MODA

PRODUCTION DATA.  

  1. Module Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. Revision History
  3. Device Comparison
    1. 3.1 Related Products
  4. Terminal Configuration and Functions
    1. 4.1 CC3220MODx and CC3220MODAx Pin Diagram
    2. 4.2 Pin Attributes
      1. Table 4-1 Module Pin Attributes
    3. 4.3 Connections for Unused Pins
    4. 4.4 Pin Attributes and Pin Multiplexing
    5. 4.5 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
    6. 4.6 Pad State After Application of Power to Chip, but Before Reset Release
  5. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Current Consumption (CC3220MODS and CC3220MODAS)
    5. 5.5  Current Consumption (CC3220MODSF and CC3220MODASF)
    6. 5.6  TX Power and IBAT Versus TX Power Level Settings
    7. 5.7  Brownout and Blackout Conditions
    8. 5.8  Electrical Characteristics
    9. 5.9  CC3220MODAx Antenna Characteristics
    10. 5.10 WLAN Receiver Characteristics
    11. 5.11 WLAN Transmitter Characteristics
    12. 5.12 Reset Requirement
    13. 5.13 Thermal Resistance Characteristics for MOB and MON Packages
    14. 5.14 Timing and Switching Characteristics
      1. 5.14.1 Power-Up Sequencing
      2. 5.14.2 Power-Down Sequencing
      3. 5.14.3 Device Reset
      4. 5.14.4 Wake Up From Hibernate Timing
      5. 5.14.5 Peripherals Timing
        1. 5.14.5.1  SPI
          1. 5.14.5.1.1 SPI Master
          2. 5.14.5.1.2 SPI Slave
        2. 5.14.5.2  I2S
          1. 5.14.5.2.1 I2S Transmit Mode
          2. 5.14.5.2.2 I2S Receive Mode
        3. 5.14.5.3  GPIOs
          1. 5.14.5.3.1 GPIO Input Transition Time Parameters
        4. 5.14.5.4  I2C
        5. 5.14.5.5  IEEE 1149.1 JTAG
        6. 5.14.5.6  ADC
        7. 5.14.5.7  Camera Parallel Port
        8. 5.14.5.8  UART
        9. 5.14.5.9  External Flash Interface
        10. 5.14.5.10 SD Host
        11. 5.14.5.11 Timers
  6. Detailed Description
    1. 6.1  Overview
    2. 6.2  Arm® Cortex®-M4 Processor Core Subsystem
    3. 6.3  Wi-Fi® Network Processor Subsystem
      1. 6.3.1 WLAN
      2. 6.3.2 Network Stack
    4. 6.4  Security
    5. 6.5  Power-Management Subsystem
      1. 6.5.1 VBAT Wide-Voltage Connection
    6. 6.6  Low-Power Operating Mode
    7. 6.7  Memory
      1. 6.7.1 Internal Memory
        1. 6.7.1.1 SRAM
        2. 6.7.1.2 ROM
        3. 6.7.1.3 Flash Memory
        4. 6.7.1.4 Memory Map
    8. 6.8  Restoring Factory Default Configuration
    9. 6.9  Boot Modes
      1. 6.9.1 Boot Mode List
    10. 6.10 Device Certification and Qualification
      1. 6.10.1 FCC Certification and Statement
      2. 6.10.2 Industry Canada (IC) Certification and Statement
      3. 6.10.3 ETSI/CE Certification
      4. 6.10.4 MIC Certification
      5. 6.10.5 SRRC Certification and Statement
    11. 6.11 Module Markings
    12. 6.12 End Product Labeling
    13. 6.13 Manual Information to the End User
  7. Applications, Implementation, and Layout
    1. 7.1 Typical Application
    2. 7.2 Device Connection and Layout Fundamentals
      1. 7.2.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.2.2 Reset
      3. 7.2.3 Unused Pins
    3. 7.3 PCB Layout Guidelines
      1. 7.3.1 General Layout Recommendations
      2. 7.3.2 CC3220MODx RF Layout Recommendations
        1. 7.3.2.1 Antenna Placement and Routing
        2. 7.3.2.2 Transmission Line Considerations
      3. 7.3.3 CC3220MODAx RF Layout Recommendations
  8. Environmental Requirements and Specifications
    1. 8.1 PCB Bending
    2. 8.2 Handling Environment
      1. 8.2.1 Terminals
      2. 8.2.2 Falling
    3. 8.3 Storage Condition
      1. 8.3.1 Moisture Barrier Bag Before Opened
      2. 8.3.2 Moisture Barrier Bag Open
    4. 8.4 Baking Conditions
    5. 8.5 Soldering and Reflow Condition
  9. Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Development Tools and Software
    3. 9.3 Firmware Updates
    4. 9.4 Device Nomenclature
    5. 9.5 Documentation Support
      1. 9.5.1 Community Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Export Control Notice
    9. 9.9 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical, Land, and Solder Paste Drawings
    2. 10.2 Package Option Addendum
      1. 10.2.1 Packaging Information
      2. 10.2.2 Tape and Reel Information
        1. 10.2.2.1 CC3220MODx Tape Specifications
        2. 10.2.2.2 CC3220MODAx Tape Specifications
          1. 10.2.2.1 CC3220MODx Tape Specifications
          2. 10.2.2.2 CC3220MODAx Tape Specifications

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • MON|63
Thermal pad, mechanical data (Package|Pins)

Pin Attributes and Pin Multiplexing

The module makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of hardware configuration (at module reset) and register control.

The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used. Table 4-4 describes the general pin attributes and presents an overview of pin multiplexing. All pin multiplexing options are configurable using the pin MUX registers. The following special considerations apply:

  • All I/Os support drive strengths of 2, 4, and 6 mA. Drive strength is individually configurable for each pin.
  • All I/Os support 10-μA pullup and pulldown resistors.
  • By default, all I/Os float in the Hibernate state. However, the default state can be changed by SW.
  • All digital I/Os are non fail-safe.

NOTE

If an external device drives a positive voltage to the signal pads and the CC3220MODx or CC3220MODAx modules are not powered, DC is drawn from the other device. If the drive strength of the external device is adequate, an unintentional wakeup and boot of the CC3220MODx or CC3220MODAx modules can occur. To prevent current draw, TI recommends any one of the following conditions:

  • All devices interfaced to CC3220MODx and CC3220MODAx modules must be powered from the same power rail as the chip.
  • Use level shifters between the device and any external devices fed from other independent rails.
  • The nRESET pin of the CC3220MODx and CC3220MODAx modules must be held low until the VBAT supply to the module is driven and stable.
  • All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other pins are left in the Hi-Z state.

Table 4-4 Pin Attributes and Pin Multiplexing

GENERAL PIN ATTRIBUTES FUNCTION PAD STATES
Pkg. Pin Pin Alias Use Select as Wakeup Source Config. Addl. Analog Mux Muxed With JTAG Dig. Pin Mux Config. Reg. Dig. Pin Mux Config. Mode Value Signal Name Signal Description Signal Direction LPDS(1) Hib(2) nRESET = 0
1 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
2 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
3 GPIO10 I/O No No No GPIO_PAD_
CONFIG_10
(0x4402 E0C8)
0 GPIO10 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
1 I2C_SCL I2C clock I/O
(open drain)
Hi-Z,
Pull,
Drive
3 GT_PWM06 Pulse-width modulated O/P O Hi-Z,
Pull,
Drive
7 UART1_TX UART TX data O 1
6 SDCARD_CLK SD card clock O 0
12 GT_CCP01 Timer capture port I Hi-Z,
Pull,
Drive
4 GPIO11 I/O Yes No No GPIO_PAD_
CONFIG_11
(0x4402 E0CC)
0 GPIO11 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
1 I2C_SDA I2C data I/O
(open drain)
Hi-Z,
Pull,
Drive
3 GT_PWM07 Pulse-width modulated O/P O Hi-Z,
Pull,
Drive
4 pXCLK (XVCLK) Free clock to parallel camera O 0
6 SDCARD_CMD SD card command line I/O
(open drain)
Hi-Z,
Pull,
Drive
7 UART1_RX UART RX data I Hi-Z,
Pull,
Drive
12 GT_CCP02 Timer capture port I Hi-Z,
Pull,
Drive
13 MCAFSX I2S audio port frame sync O Hi-Z,
Pull,
Drive
5 GPIO14 I/O No No No GPIO_PAD_
CONFIG_14
(0x4402 E0D8)
0 GPIO14 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
5 I2C_SCL I2C clock I/O
(open drain)
7 GSPI_CLK General SPI clock I/O
4 pDATA8 (CAM_D4) Parallel camera data bit 4 I
12 GT_CCP05 Timer capture port I
6 GPIO15 I/O No No No GPIO_PAD_
CONFIG_15
(0x4402 E0DC)
0 GPIO15 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
5 I2C_SDA I2C data I/O
(open drain)
7 GSPI_MISO General SPI MISO I/O
4 pDATA9 (CAM_D5) Parallel camera data bit 5 I
13 GT_CCP06 Timer capture port I
8 SDCARD_
DATA0
SD card data I/O
7 GPIO16 I/O No No No GPIO_PAD_
CONFIG_16
(0x4402 E0E0)
0 GPIO16 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
7 GSPI_MOSI General SPI MOSI I/O Hi-Z,
Pull,
Drive
4 pDATA10 (CAM_D6) Parallel camera data bit 6 I Hi-Z,
Pull,
Drive
5 UART1_TX UART1 TX data O 1
13 GT_CCP07 Timer capture port I Hi-Z,
Pull,
Drive
8 SDCARD_CLK SD card clock O Zero
8 GPIO17 I/O Yes No No GPIO_PAD_
CONFIG_17
(0x4402 E0E4)
0 GPIO17 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
5 UART1_RX UART1 RX data I
7 GSPI_CS General SPI chip select I/O
4 pDATA11 (CAM_D7) Parallel camera data bit 7 I
8 SDCARD_
CMD
SD card command line I/O
9 GPIO12 I/O No No No GPIO_PAD_
CONFIG_12
(0x4402 E0D0)
0 GPIO12 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
3 McACLK I2S audio port clock output O Hi-Z,
Pull,
Drive
4 pVS (VSYNC) Parallel camera vertical sync I Hi-Z,
Pull,
Drive
5 I2C_SCL I2C clock I/O
(open drain)
Hi-Z,
Pull,
Drive
7 UART0_TX UART0 TX data O 1
12 GT_CCP03 Timer capture port I Hi-Z,
Pull,
Drive
10 GPIO13 I/O Yes No No GPIO_PAD_
CONFIG_13
(0x4402 E0D4)
0 GPIO13 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
5 I2C_SDA I2C data I/O
(open drain)
4 pHS (HSYNC) Parallel camera horizontal sync I
7 UART0_RX UART0 RX data I
12 GT_CCP04 Timer capture port I
11 GPIO22 I/O No No No GPIO_PAD_
CONFIG_22
(0x4402 E0F8)
0 GPIO22 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
7 McAFSX I2S audio port frame sync O
5 GT_CCP04 Timer capture port I
12 JTAG_TDI I/O No No Muxed with JTAG TDI GPIO_PAD_
CONFIG_23
(0x4402 E0FC)
1 TDI JTAG TDI. Reset default pinout. I Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
0 GPIO23 GPIO I/O
2 UART1_TX UART1 TX data O 1
9 I2C_SCL I2C clock I/O
(open drain)
Hi-Z,
Pull,
Drive
13 FLASH_
SPI_
MISO
N/A N/A N/A N/A N/A N/A FLASH_SPI_MISO Data from SPI serial Flash (fixed default) N/A Hi-Z Hi-Z Hi-Z
14 FLASH_
SPI_
nCS_IN
N/A N/A N/A N/A N/A N/A FLASH_SPI_nCS_IN Chip select to SPI serial Flash (fixed default) N/A 1 Hi-Z,
Pull,
Drive
Hi-Z
15 FLASH_
SPI_CLK
N/A N/A N/A N/A N/A N/A FLASH_SPI_
CLK
Clock to SPI serial Flash (fixed default) N/A Hi-Z,
Pull,
Drive (3)
Hi-Z,
Pull,
Drive
Hi-Z
16 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
17 FLASH_
SPI_
MOSI
N/A N/A N/A N/A N/A N/A FLASH_SPI_MOSI Data to SPI serial Flash (fixed default) N/A Hi-Z,
Pull,
Drive (3)
Hi-Z,
Pull,
Drive
Hi-Z
18 JTAG_TDO I/O Yes No Muxed with JTAG TDO GPIO_PAD_
CONFIG_ 24
(0x4402 E100)
1 TDO JTAG TDO. Reset default pinout. O Hi-Z,
Pull,
Drive
Driven high in SWD; driven low in 4-wire JTAG Hi-Z
0 GPIO24 GPIO I/O
5 PWM0 Pulse-width modulated O/P O
2 UART1_RX UART1 RX data I
9 I2C_SDA I2C data I/O
(open drain)
4 GT_CCP06 Timer capture port I
6 McAFSX I2S audio port frame sync O
19 GPIO28 I/O No No No GPIO_PAD_
CONFIG_ 40
(0x4402 E140)
0 GPIO28 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
20 NC WLAN analog N/A N/A N/A N/A N/A NC Reserved N/A N/A N/A N/A
21 JTAG_TCK I/O No No Muxed with JTAG/
SWD-TCK
GPIO_PAD_
CONFIG_ 28
(0x4402 E110)
1 TCK JTAG/SWD TCK.
Reset default pinout.
I Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
8 GT_PWM03 Pulse-width modulated O/P O
22 JTAG_TMS I/O No No Muxed with JTAG/
SWD-TMSC
GPIO_PAD_
CONFIG_ 29
(0x4402 E114)
1 TMS JTAG/SWD TMS.
Reset default pinout.
I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
0 GPIO29 GPIO
23(4) SOP2 O only No No No GPIO_PAD_
CONFIG_ 25
(0x4402 E104)
0 GPIO25 GPIO O Hi-Z,
Pull,
Drive
Driven Low Hi-Z
9 GT_PWM02 Pulse-width modulated O/P O Hi-Z,
Pull,
Drive
2 McAFSX I2S audio port frame sync O Hi-Z,
Pull,
Drive
See (5) TCXO_EN Enable to optional external 40-MHz TCXO O 0
See (6) SOP2 Sense-on-power 2 I Hi-Z,
Pull,
Drive
24 SOP1 Config sense N/A N/A N/A N/A N/A SOP1 Sense-on-power 1 N/A N/A N/A N/A
25(7) ANT_SEL1 O only No User config not required
(8)
No GPIO_PAD_
CONFIG_26
(0x4402 E108)
0 ANTSEL1(3) Antenna selection control O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
26(7) ANT_SEL2 O only No User config not required
(8)
No GPIO_PAD_
CONFIG_27
(0x4402 E10C)
0 ANTSEL2(3) Antenna selection control O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
27 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
28 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
29 NC WLAN analog N/A N/A N/A N/A N/A NC Reserved N/A N/A N/A N/A
30 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
31 RF_BG WLAN analog N/A N/A N/A N/A N/A CC3220MODx:
RF BG band
CC3220MODAx: NC
N/A N/A N/A N/A N/A
32 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
33 NC WLAN analog N/A N/A N/A N/A NC Reserved
34 SOP0 Config sense N/A N/A N/A N/A N/A SOP0 Sense-on-power 0 N/A N/A N/A N/A
35 nRESET Global reset N/A N/A N/A N/A N/A nRESET Master chip reset. Active low. N/A N/A N/A N/A
36 VBAT_
RESET
Global reset N/A N/A N/A N/A N/A VBAT_RESET VBAT to nRESET pullup resistor N/A N/A N/A N/A
37 VBAT1 Supply input N/A N/A N/A N/A N/A VBAT1 Analog DC/DC input (connected to chip input supply [VBAT]) N/A N/A N/A N/A
38 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
39 NC WLAN analog N/A N/A N/A N/A N/A NC Reserved N/A N/A N/A N/A
40 VBAT2 Supply input N/A N/A N/A N/A N/A VBAT2 Analog input supply VBAT N/A N/A N/A N/A
41 NC WLAN analog N/A N/A N/A N/A N/A NC Reserved N/A N/A N/A N/A
42 GPIO30 I/O No User config not required
(8)
No GPIO_PAD_
CONFIG_30
(0x4402 E118)
0 GPIO30 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
9 UART0_TX UART0 TX data O 1
2 McACLK I2S audio port clock O Hi-Z,
Pull,
Drive
3 McAFSX I2S audio port frame sync O Hi-Z,
Pull,
Drive
4 GT_CCP05 Timer capture port I Hi-Z,
Pull,
Drive
7 GSPI_MISO General SPI MISO I/O Hi-Z,
Pull,
Drive
43 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
44 GPIO0 I/O No User config not required
(8)
No GPIO_PAD_
CONFIG_0
(0x4402 E0A0)
0 GPIO0 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
12 UART0_CTS UART0 Clear-to-Send input (active low) I Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
6 McAXR1 I2S audio port data 1 (RX/TX) I/O Hi-Z,
Pull,
Drive
7 GT_CCP00 Timer capture port I Hi-Z,
Pull,
Drive
9 GSPI_CS General SPI chip select I/O Hi-Z,
Pull,
Drive
10 UART1_RTS UART1 Request-to-Send (active low) O 1
3 UART0_RTS UART0 Request-to-Send (active low) O 1
4 McAXR0 I2S audio port data 0 (RX/TX) I/O Hi-Z,
Pull,
Drive
45 NC WLAN analog N/A N/A N/A N/A N/A NC Reserved N/A N/A N/A N/A
46 GPIO1 I/O No No No GPIO_PAD_
CONFIG_1
(0x4402 E0A4)
0 GPIO1 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
3 UART0_TX UART0 TX data O 1
4 pCLK (PIXCLK) Pixel clock from parallel camera sensor I Hi-Z,
Pull,
Drive
6 UART1_TX UART1 TX data O 1
7 GT_CCP01 Timer capture port I Hi-Z,
Pull,
Drive
47(10) GPIO2 Analog input (up to 1.8 V)/ digital I/O Yes See (9) No GPIO_PAD_
CONFIG_2
(0x4402 E0A8)
See (5) ADC_CH0 ADC channel 0 input (1.5-V max) I Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
0 GPIO2 GPIO I/O Hi-Z,
Pull,
Drive
3 UART0_RX UART0 RX data I Hi-Z,
Pull,
Drive
6 UART1_RX UART1 RX data I Hi-Z,
Pull,
Drive
7 GT_CCP02 Timer capture port I Hi-Z,
Pull,
Drive
48(10) GPIO3 Analog input (up to 1.8 V)/ digital I/O No See (9) No GPIO_PAD_
CONFIG_3
(0x4402 E0AC)
See (5) ADC_CH1 ADC channel 1 input (1.5-V max) I Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
0 GPIO3 GPIO I/O Hi-Z,
Pull,
Drive
6 UART1_TX UART1 TX data O 1
4 pDATA7 (CAM_D3) Parallel camera data bit 3 I Hi-Z,
Pull,
Drive
49(10) GPIO4 Analog input (up to 1.8 V)/ digital I/O Yes See (9) Yes GPIO_PAD_
CONFIG_4
(0x4402 E0B0)
See(5) ADC_CH2 ADC channel 2 input (1.5-V max) I Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
0 GPIO4 GPIO I/O Hi-Z,
Pull,
Drive
6 UART1_RX UART1 RX data I Hi-Z,
Pull,
Drive
4 pDATA6 (CAM_D2) Parallel camera data bit 2 I Hi-Z,
Pull,
Drive
50(10) GPIO5 Analog input up to 1.5 V No See(9) No GPIO_PAD_
CONFIG_5
(0x4402 E0B4)
See(5) ADC_CH3 ADC channel 3 input (1.5 V max) I i-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
0 GPIO5 GPIO I/O Hi-Z,
Pull,
Drive
4 pDATA5 (CAM_D1) Parallel camera data bit 1 I Hi-Z,
Pull,
Drive
6 McAXR1 I2S audio port data 1 (RX, TX) I/O Hi-Z,
Pull,
Drive
7 GT_CCP05 Timer capture port I Hi-Z,
Pull,
Drive
51 GPIO6 I/O No No No GPIO_PAD_
CONFIG_6
(0x4402 E0B8)
0 GPIO6 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
5 UART0_RTS UART0 Request-to-Send (active low) O 1
4 pDATA4 (CAM_D0) Parallel camera data bit 0 I Hi-Z,
Pull,
Drive
3 UART1_CTS UART1 Clear to send (active low) I Hi-Z,
Pull,
Drive
6 UART0_CTS UART0 Clear to send (active low) I Hi-Z,
Pull,
Drive
7 GT_CCP06 Timer capture port I Hi-Z,
Pull,
Drive
52 GPIO7 I/O No No No GPIO_PAD_
CONFIG_7
(0x4402 E0BC)
0 GPIO7 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
13 McACLK I2S audio port clock O Hi-Z,
Pull,
Drive
3 UART1_RTS UART1 Request to send (active low) O 1
10 UART0_RTS UART0 Request to send (active low) O 1
11 UART0_TX UART0 TX data O 1
53 GPIO8 I/O No No No GPIO_PAD_
CONFIG_8
(0x4402 E0C0)
0 GPIO8 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
6 SDCARD_IRQ Interrupt from SD card (future support) I
7 McAFSX I2S audio port frame sync O
12 GT_CCP06 Timer capture port I
54 GPIO9 I/O No No No GPIO_PAD_
CONFIG_9
(0x4402 E0C4)
0 GPIO9 GPIO I/O Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
3 GT_PWM05 Pulse-width modulated O/P O
6 SDCARD_
DATA0
SD card data I/O
7 McAXR0 I2S audio port data (RX, TX) I/O
12 GT_CCP00 Timer capture port I
55 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
56 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
57 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
58 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
59 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
60 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
61 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
62 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
63 GND GND N/A N/A N/A N/A N/A GND GND N/A N/A N/A N/A
  1. LPDS state: The state of unused I/Os is Hi-Z. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
  2. Hibernate mode: The state of the I/Os is Hi-Z. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
  3. To minimize leakage in some serial Flash vendors during LPDS, TI recommends that the user application always enables internal weak pulldowns on FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.
  4. Pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
  5. For details on proper use, see Drive Strength and Reset States for Analog-Digital Multiplexed Pins.
  6. Pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the chip hardware power-up mode. For this reason, the pin must be output only when used for digital functions.
  7. This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220MODx module between two antennas. These pins must not be used for other functionalities.
  8. Device firmware automatically enables the digital path during ROM boot.
  9. Requires user configuration to enable the analog switch of the ADC channel. (Switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC switch.
  10. Pin is shared by the ADC inputs and digital I/O pad cells.
  11. NOTE

    The ADC inputs are tolerant up to 1.8 V (see Section 5.14.5.6 for further details on the useable range of the ADC). The digital pads can tolerate up to 3.6 V. Hence, take care to prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the digital I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter disabling the respective pass switches (S7 [Pin 47], S8 [Pin 48], S9 [Pin 49], and S10 [Pin 50]). For more information, see Section 4.5.