SCHS047I August   1998  – September 2017 CD4051B , CD4052B , CD4053B

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Functional Diagrams of CD405xB
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions CD4051B
    2.     Pin Functions CD4052B
    3.     Pin Functions CD4053B
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Performance Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • NS|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Wide Range of Digital and Analog Signal Levels
    • Digital: 3 V to 20 V
    • Analog: ≤ 20 VP-P
  • Low ON Resistance, 125 Ω (Typical) Over 15 VP-P Signal Input Range for VDD – VEE = 18 V
  • High OFF Resistance, Channel Leakage of
    ±100 pA (Typical) at VDD – VEE = 18 V
  • Logic-Level Conversion for Digital Addressing Signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V) to Switch Analog Signals to 20 VP-P (VDD – VEE = 20 V) Matched Switch Characteristics, rON = 5 Ω (Typical) for VDD – VEE = 15 V Very Low Quiescent Power Dissipation Under All Digital-Control Input and Supply Conditions, 0.2 µW (Typical) at
    VDD – VSS = VDD – VEE = 10 V
  • Binary Address Decoding on Chip
  • 5 V, 10 V, and 15 V Parametric Ratings
  • 100% Tested for Quiescent Current at 20 V
  • Maximum Input Current of 1 µA at 18 V Over Full Package Temperature Range, 100 nA at 18 V and 25°C
  • Break-Before-Make Switching Eliminates Channel Overlap