SLPS223F Data sheet

SLPS223F May 2010 – October 2016 CSD86350Q5D

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DQY|8

Thermal pad, mechanical data (Package|Pins)

Orderable Information

slps223f_pm

5 Specifications

5.1 Absolute Maximum Ratings

T_A = 25°C (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	V_IN to P_GND	–0.8	25	V
	T_G to T_GR	–8	10
	B_G to P_GND	–8	10
Pulsed current rating, I_DM⁽²⁾			120	A
Power dissipation, P_D			13	W
Avalanche energy, E_AS	Sync FET, I_D = 100 A, L = 0.1 mH		500	mJ
Avalanche energy, E_AS	Control FET, I_D = 58 A, L = 0.1 mH		168	mJ
Operating junction, T_J		–55	150	°C
Storage temperature, T_STG		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Pulse duration ≤ 50 µs, duty cycle ≤ 1%.

5.2 Recommended Operating Conditions

T_A = 25° (unless otherwise noted)

			MIN	MAX	UNIT
V_GS	Gate drive voltage		4.5	8	V
V_IN	Input supply voltage			22	V
f_SW	Switching frequency	C_BST = 0.1 μF (min)	200	1500	kHz
	Operating current			40	A
T_J	Operating temperature			125	°C

5.3 Thermal Information

T_A = 25°C (unless otherwise stated)

THERMAL METRIC		MAX	UNIT
R_θJA	Junction-to-ambient thermal resistance (min Cu)⁽¹⁾⁽²⁾	102	°C/W
R_θJA	Junction-to-ambient thermal resistance (max Cu)⁽¹⁾⁽²⁾	50	°C/W
R_θJC	Junction-to-case thermal resistance (top of package)⁽²⁾	20	°C/W
R_θJC	Junction-to-case thermal resistance (P_GND pin)⁽²⁾	2	°C/W

(1) Device mounted on FR4 material with 1-in² (6.45-cm²) Cu.

(2) R_θJC is determined with the device mounted on a 1-in² (6.45-cm²), 2 oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. R_θJC is specified by design while R_θJA is determined by the user’s board design.

5.4 Power Block Performance

T_A = 25° (unless otherwise noted)

PARAMETER		CONDITIONS	MIN	TYP	MAX	UNIT
P_LOSS	Power loss⁽¹⁾	V_IN = 12 V, V_GS = 5 V, V_OUT = 1.3 V, I_OUT = 25 A, f_SW = 500 kHz, L_OUT = 0.3 µH, T_J = 25°C		2.8		W
I_QVIN	V_INquiescent current	T_G to T_GR = 0 V B_Gto P_GND = 0 V		10		µA

(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_IN to P_GND pins and using a high-current 5-V driver IC.

5.5 Electrical Characteristics

T_A = 25°C (unless otherwise stated)

PARAMETER		TEST CONDITIONS	Q1 Control FET			Q2 Sync FET			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
STATIC CHARACTERISTICS
BV_DSS	Drain-to-source voltage	V_GS = 0 V, I_DS = 250 μA	25			25			V
I_DSS	Drain-to-source leakage current	V_GS = 0 V, V_DS = 20 V			1			1	μA
I_GSS	Gate-to-source leakage current	V_DS = 0 V, V_GS = +10 / –8 V			100			100	nA
V_GS(th)	Gate-to-source threshold voltage	V_DS = V_GS, I_DS = 250 μA	0.9	1.4	2.1	0.9	1.1	1.6	V
Z_DS(on)	Drain-to-source on impedance	V_IN = 12 V, V_DD = 5 V, V_OUT = 1.3 V, I_OUT = 25 A, f_SW = 500 kHz, L_OUT = 0.3 µH		5			1.1		mΩ
g_fs	Transconductance	V_DS = 10 V, I_DS = 20 A		103			132		S
DYNAMIC CHARACTERISTICS
C_ISS	Input capacitance⁽¹⁾	V_GS = 0 V, V_DS = 12.5 V, f = 1 MHz		1440	1870		3080	4000	pF
C_OSS	Output capacitance⁽¹⁾			645	840		1550	2015	pF
C_RSS	Reverse transfer capacitance⁽¹⁾			22	29		45	59	pF
R_G	Series gate resistance⁽¹⁾			1.4	2.8		1.4	2.8	Ω
Q_g	Gate charge total (4.5 V)⁽¹⁾	V_DS = 12.5 V, I_DS = 20 A		8.2	10.7		19.4	25	nC
Q_gd	Gate charge – gate-to-drain			1			2.5		nC
Q_gs	Gate charge – gate-to-source			3.2			5.1		nC
Q_g(th)	Gate charge at V_th			1.9			2.8		nC
Q_OSS	Output charge	V_DS = 12 V, V_GS = 0 V		9.9			28		nC
t_d(on)	Turnon delay time	V_DS = 12.5 V, V_GS = 4.5 V, I_DS = 20 A, R_G = 2 Ω		8			9		ns
t_r	Rise time			21			23		ns
t_d(off)	Turnoff delay time			9			24		ns
t_f	Fall time			2.3			21		ns
DIODE CHARACTERISTICS
V_SD	Diode forward voltage	I_DS = 20 A, V_GS = 0 V		0.85	1		0.77	1	V
Q_rr	Reverse recovery charge	V_dd = 12 V, I_F = 20 A, di/dt = 300 A/μs		16			40		nC
t_rr	Reverse recovery time	V_dd = 12 V, I_F = 20 A, di/dt = 300 A/μs		22			32		ns

(1) Specified by design.

Max R_θJA = 50°C/W when mounted on 1-in² (6.45-cm²) of 2-oz (0.071-mm) thick Cu.

Max R_θJA = 102°C/W when mounted on minimum pad area of 2-oz (0.071-mm) thick Cu.

5.6 Typical Power Block Device Characteristics

T_J = 125°C, unless stated otherwise.

Figure 1. Power Loss vs Output Current

Figure 3. Safe Operating Area – PCB Vertical Mount ⁽¹⁾

Figure 5. Typical Safe Operating Area ⁽¹⁾

(1)The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) x 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Application and Implementation for detailed explanation.