SLPS665 March   2018 CSD86356Q5D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Top View
      1.      Device Images
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics – Q1 Control FET
    6. 5.6 Electrical Characteristics – Q2 Sync FET
    7. 5.7 Typical Power Block Device Characteristics
    8. 5.8 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
        1. 6.1.1.1 Comparison of RDS(ON) vs ZDS(ON)
      2. 6.1.2 Power Loss Curves
      3. 6.1.3 Safe Operating Area (SOA) Curves
      4. 6.1.4 Normalized Curves
    2. 6.2 Typical Application
      1. 6.2.1 Design Example: Calculating Power Loss and SOA
      2. 6.2.2 Operating Conditions
        1. 6.2.2.1 Calculating Power Loss
        2. 6.2.2.2 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Recommended Schematic Overview
    2. 7.2 Recommended PCB Design Overview
      1. 7.2.1 Electrical Performance
      2. 7.2.2 Thermal Performance
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q5D Package Dimensions
    2. 9.2 Pin Configuration
    3. 9.3 Land Pattern Recommendation
    4. 9.4 Stencil Recommendation

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics – Q1 Control FET

Tj = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 µA 25 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 20 V 1 µA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = +10 / –8 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 µA 0.95 1.85 V
ZDS(on) Effective AC on-impedance VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,
IOUT = 20 A, ƒSW = 500 kHz,
LOUT = 300 nH		 4.5 mΩ
gfs Transconductance VDS = 2.5 V, IDS = 20 A 70 S
DYNAMIC CHARACTERISTICS
CISS Input capacitance VGS = 0 V, VDS = 12.5 V, ƒ = 1 Mhz 803 1040 pF
COSS Output capacitance 548 712 pF
CRSS Reverse transfer capacitance 27 35 pF
RG Series gate resistance 2.1 4.2 Ω
Qg Gate charge total (4.5 V) VDS = 12.5 V, IDS = 20 A 6.0 7.9 nC
Qgd Gate charge – gate-to-drain 1.3 nC
Qgs Gate charge – gate-to-source 2.6 nC
Qg(th) Gate charge at Vth 1.2 nC
QOSS Output charge VDS = 12.5 V, VGS = 0 V 10.3 nC
td(on) Turn on delay time VDS = 12.5 V, VGS = 4.5 V, IDS = 20 A,
RG = 0 Ω		 7 ns
tr Rise time 26 ns
td(off) Turn off delay time 12 ns
tf Fall time 3 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage IDS = 20 A, VGS = 0 V 0.84 0.95 V
Qrr Reverse recovery charge VDD = 12.5 V, IF = 20 A, di/dt = 300 A/µs 34 nC
trr Reverse recovery time 23 ns