SLPS665
March 2018
CSD86356Q5D
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Top View
Device Images
4
Revision History
5
Specifications
5.1
Absolute Maximum Ratings
5.2
Recommended Operating Conditions
5.3
Thermal Information
5.4
Power Block Performance
5.5
Electrical Characteristics – Q1 Control FET
5.6
Electrical Characteristics – Q2 Sync FET
5.7
Typical Power Block Device Characteristics
5.8
Typical Power Block MOSFET Characteristics
6
Application and Implementation
6.1
Application Information
6.1.1
Equivalent System Performance
6.1.1.1
Comparison of RDS(ON) vs ZDS(ON)
6.1.2
Power Loss Curves
6.1.3
Safe Operating Area (SOA) Curves
6.1.4
Normalized Curves
6.2
Typical Application
6.2.1
Design Example: Calculating Power Loss and SOA
6.2.2
Operating Conditions
6.2.2.1
Calculating Power Loss
6.2.2.2
Calculating SOA Adjustments
7
Layout
7.1
Recommended Schematic Overview
7.2
Recommended PCB Design Overview
7.2.1
Electrical Performance
7.2.2
Thermal Performance
8
Device and Documentation Support
8.1
Receiving Notification of Documentation Updates
8.2
Community Resources
8.3
Trademarks
8.4
Electrostatic Discharge Caution
8.5
Glossary
9
Mechanical, Packaging, and Orderable Information
9.1
Q5D Package Dimensions
9.2
Pin Configuration
9.3
Land Pattern Recommendation
9.4
Stencil Recommendation
Package Options
Mechanical Data (Package|Pins)
DMV|8
MPSS092
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slps665_oa
slps665_pm
9.1
Q5D Package Dimensions
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.