SLPS350A February   2014  – January 2017 CSD87333Q3D

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6 Applications
    1. 6.1 Power Loss Curves
    2. 6.2 Safe Operating Area (SOA) Curves
    3. 6.3 Normalized Curves
    4. 6.4 Calculating Power Loss and SOA
      1. 6.4.1 Design Example
      2. 6.4.2 Calculating Power Loss
      3. 6.4.3 Calculating SOA Adjustments
  7. 7 Recommended PCB Design Overview
    1. 7.1 Electrical Performance
  8. 8 Thermal Performance
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Community Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Q3D Package Dimensions
    2. 10.2 Pinout Configuration
    3. 10.3 Land Pattern Recommendation
    4. 10.4 Stencil Recommendation
    5. 10.5 Q3D Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings(1)

TA = 25°C (unless otherwise noted)
PARAMETER CONDITIONS MIN MAX UNIT
Voltage VIN to PGND –0.8 30 V
VSW to PGND 30 V
VSW to PGND (10 ns) 32 V
TG to TGR –0.3 10 V
BG to PGND –0.3 10 V
Pulsed current rating, IDM(2) 40 A
Power dissipation, PD 6 W
Avalanche energy, EAS Sync FET, ID = 19, L = 0.1 mH 18 mJ
Control FET, ID = 19, L = 0.1 mH 18
Operating junction temperature, TJ –55 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse duration ≤ 50 µS. Duty cycle ≤ 0.01%.

5.2 Recommended Operating Conditions

TA = 25°C (unless otherwise noted)
PARAMETER CONDITIONS MIN MAX UNIT
VGS Gate drive voltage 3.3 8 V
VIN Input supply voltage 24 V
fSW Switching frequency CBST = 0.1 µF (min) 1500 kHz
Operating current 15 A
TJ Operating temperature 125 °C

5.3 Power Block Performance(1)

TA = 25°C (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
PLOSS Power loss(1) VIN = 12 V, VGS = 5 V, VOUT = 3.3 V,
IOUT = 8 A, fSW = 500 kHz,
LOUT = 1 µH, TJ = 25°C		 1.5 W
IQVIN VIN quiescent current TG to TGR = 0 V BG to PGND = 0 V 10 µA
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5-V driver IC.

5.4 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance (min Cu)(2) 150 °C/W
Junction-to-ambient thermal resistance (max Cu)(2)(1) 80
RθJC Junction-to-case thermal resistance (top of package)(2) 36 °C/W
Junction-to-case thermal resistance (PGND pin)(2) 3.7
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
(2) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design.

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS Q1 Control FET Q2 Sync FET UNIT
MIN TYP MAX MIN TYP MAX
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 µA 30 30 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 20 V 1 1 µA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = +10 / –8 V 100 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 µA 0.75 0.95 1.20 0.75 0.95 1.20 V
RDS(on) Drain-to-source on resistance VGS = 3.5 V, IDS = 4 A 14.7 17.7 14.7 17.7 mΩ
VGS = 4.5 V, IDS = 4 A 13.4 16.1 13.4 16.1
VGS = 8 V, IDS = 4 A 11.9 14.3 11.9 14.3
gfs Transconductance VDS = 15 V, IDS = 4 A 43 43 S
DYNAMIC CHARACTERISTICS
CISS Input capacitance VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz		 509 662 509 662 pF
COSS Output capacitance 222 289 222 289 pF
CRSS Reverse transfer capacitance 8.2 10.7 8.2 10.7 pF
RG Series gate resistance 3.4 6.8 3.4 6.8 Ω
Qg Gate charge total (4.5 V) VDS = 15 V,
IDS = 4 A		 3.5 4.6 3.5 4.6 nC
Qgd Gate charge gate-to-drain 0.3 0.3 nC
Qgs Gate charge gate-to-source 1.6 1.6 nC
Qg(th) Gate charge at Vth 0.6 0.6 nC
QOSS Output charge VDS = 15 V, VGS = 0 V 5.3 5.3 nC
td(on) Turnon delay time VDS = 15 V, VGS = 4.5 V,
IDS = 4 A, RG = 2 Ω		 2.1 2.1 ns
tr Rise time 3.9 3.9 ns
td(off) Turnoff delay time 9.4 9.4 ns
tf Fall time 2.2 2.2 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage IDS = 4 A, VGS = 0 V 0.80 1.0 0.80 1.0 V
Qrr Reverse recovery charge VDS = 15 V, IF = 4 A,
di/dt = 300 A/µs		 10 10 nC
trr Reverse recovery time 11 11 ns
CSD87333Q3D M0205-01_LPS264.gif
Max RθJA = 80°C/W when mounted on 1 in2 (6.45 cm2) of 2-oz (0.071-mm) thick Cu.
CSD87333Q3D M0206-01_LPS264.gif
Max RθJA = 150°C/W when mounted on minimum pad area of 2-oz (0.071-mm) thick Cu.

5.6 Typical Power Block Device Characteristics

The typical power block system characteristic curves (Figure 1 through Figure 9) are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Applications for detailed explanation. TA = 125°C, unless stated otherwise.
CSD87333Q3D graph01_SLPS350.png
Figure 1. Power Loss vs Output Current
CSD87333Q3D graph03_SLPS350.png
Figure 3. Safe Operating Area – PCB Horizontal Mount
CSD87333Q3D graph05_SLPS350.png
Figure 5. Typical Safe Operating Area
CSD87333Q3D graph02_SLPS350.png
Figure 2. Power Loss vs Temperature
CSD87333Q3D graph04_SLPS350.png
Figure 4. Safe Operating Area – PCB Vertical Mount
CSD87333Q3D graph06F_SLPS350.png
Figure 6. Normalized Power Loss vs Switching Frequency
CSD87333Q3D graph08F2_LPS284.png
Figure 8. Normalized Power Loss vs Output Voltage
CSD87333Q3D graph07F_SLPS350.png
Figure 7. Normalized Power Loss vs Input Voltage
CSD87333Q3D graph09F2_SLPS350.png
Figure 9. Normalized Power Loss vs Output Inductance

5.7 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise.
CSD87333Q3D graph10_SLPS350.png
Figure 10. MOSFET Saturation Characteristics
CSD87333Q3D graph12F_SLPS350.png
Figure 12. MOSFET Gate Charge
CSD87333Q3D graph14_SLPS350.png
Figure 14. MOSFET VGS(th)
CSD87333Q3D graph16_SLPS350.png
Figure 16. MOSFET Normalized RDS(on)
CSD87333Q3D graph18_SLPS350.png
Figure 18. MOSFET Unclamped Inductive Switching
CSD87333Q3D graph11_SLPS350.png
Figure 11. MOSFET Transfer Characteristics
CSD87333Q3D graph13_SLPS350.png
Figure 13. MOSFET Capacitance
CSD87333Q3D graph15F_SLPS350.png
Figure 15. MOSFET RDS(on) vs VGS
CSD87333Q3D graph17_SLPS350.png
Figure 17. MOSFET Body Diode