UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The CLR pin is an asynchronous input pin to the DAC. When activated, this level-sensitive pin clears the DAC buffers and DAC latches to the DAC-CLEAR-DATA bits (address 03h). The device exits clear mode on the SYNC rising edge of the next valid write to the device. If the CLR pin receives a logic 0 during a write sequence during normal operation, the clear mode is activated and the buffer and DAC registers are immediately cleared. The DAC registers can also be cleared using the SCLR bit (address 04h, B5); the contents are cleared at the rising edge of SYNC.