SLAS748F March   2011  – August 2015 DAC3482

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Digital Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Electrical Characteristics - Phase-Locked Loop Specifications
    9. 6.9  Timing Requirements - Digital Specifications
    10. 6.10 Switching Characteristics - AC Specifications
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Serial Interface
      2. 7.3.2  Data Interface
        1. 7.3.2.1 Word-Wide Format
        2. 7.3.2.2 Byte-Wide Format
      3. 7.3.3  Input FIFO
      4. 7.3.4  FIFO Modes of Operation
        1. 7.3.4.1 Dual Sync Source Mode
        2. 7.3.4.2 Single Sync Source Mode
        3. 7.3.4.3 Bypass Mode
      5. 7.3.5  Clocking Modes
        1. 7.3.5.1 PLL Bypass Mode
        2. 7.3.5.2 PLL Mode
      6. 7.3.6  FIR Filters
      7. 7.3.7  Complex Signal Mixer
        1. 7.3.7.1 Full Complex Mixer
        2. 7.3.7.2 Coarse Complex Mixer
        3. 7.3.7.3 Mixer Gain
        4. 7.3.7.4 Real Channel Upconversion
      8. 7.3.8  Quadrature Modulation Correction (QMC)
        1. 7.3.8.1 Gain and Phase Correction
        2. 7.3.8.2 Offset Correction
        3. 7.3.8.3 Group Delay Correction
      9. 7.3.9  Temperature Sensor
      10. 7.3.10 Data Pattern Checker
      11. 7.3.11 Parity Check Test
        1. 7.3.11.1 Word-by-Word Parity
        2. 7.3.11.2 Block Parity
      12. 7.3.12 DAC3482 Alarm Monitoring
      13. 7.3.13 LVPECL Inputs
      14. 7.3.14 LVDS Inputs
      15. 7.3.15 Unused LVDS Port Termination
      16. 7.3.16 CMOS Digital Inputs
      17. 7.3.17 Reference Operation
      18. 7.3.18 DAC Transfer Function
      19. 7.3.19 Analog Current Outputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Multi-Device Synchronization
        1. 7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
        2. 7.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
        3. 7.4.1.3 Multi-Device Operation: Single Sync Source Mode
    5. 7.5 Programming
      1. 7.5.1 Power-Up Sequence
      2. 7.5.2 Example Start-Up Routine
        1. 7.5.2.1 Device Configuration
        2. 7.5.2.2 PLL Configuration
        3. 7.5.2.3 NCO Configuration
        4. 7.5.2.4 Example Start-Up Sequence
    6. 7.6 Register Map
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  Register Name: config0 - Address: 0x00, Default: 0x049C
        2. 7.6.1.2  Register Name: config1 - Address: 0x01, Default: 0x050E
        3. 7.6.1.3  Register Name: config2 - Address: 0x02, Default: 0x7000
        4. 7.6.1.4  Register Name: config3 - Address: 0x03, Default: 0xF000
        5. 7.6.1.5  Register Name: config4 - Address: 0x04, Default: No RESET Value (WRITE TO CLEAR)
        6. 7.6.1.6  Register Name: config5 - Address: 0x05, Default: Setup and Power-Up Conditions Dependent (WRITE TO CLEAR)
        7. 7.6.1.7  Register Name: config6 - Address: 0x06, Default: No RESET Value (READ ONLY)
        8. 7.6.1.8  Register Name: config7 - Address: 0x07, Default: 0xFFFF
        9. 7.6.1.9  Register Name: config8 - Address: 0x08, Default: 0x0000 (CAUSES AUTO-SYNC)
        10. 7.6.1.10 Register Name: config9 - Address: 0x09, Default: 0x8000
        11. 7.6.1.11 Register Name: config10 - Address: 0x0A, Default: 0x0000
        12. 7.6.1.12 Register Name: config11 - Address: 0x0B, Default: 0x0000
        13. 7.6.1.13 Register Name: config12 - Address: 0x0C, Default: 0x0400
        14. 7.6.1.14 Register Name: config13 - Address: 0x0D, Default: 0x0400
        15. 7.6.1.15 Register Name: config14 - Address: 0x0E, Default: 0x0400
        16. 7.6.1.16 Register Name: config15 - Address: 0x0F, Default: 0x0400
        17. 7.6.1.17 Register Name: config16 - Address: 0x10, Default: 0x0000 (CAUSES AUTO-SYNC)
        18. 7.6.1.18 Register Name: config17 - Address: 0x11, Default: 0x0000
        19. 7.6.1.19 Register Name: config18 - Address: 0x12, Default: 0x0000 (CAUSES AUTO-SYNC)
        20. 7.6.1.20 Register Name: config19 - Address: 0x13, Default: 0x0000
        21. 7.6.1.21 Register Name: config20 - Address: 0x14, Default: 0x0000
        22. 7.6.1.22 Register Name: config21 - Address: 0x15, Default: 0x0000
        23. 7.6.1.23 Register name: config22 - Address: 0x16, Default: 0x0000
        24. 7.6.1.24 Register Name: config23 - Address: 0x17, Default: 0x0000
        25. 7.6.1.25 Register Name: config24 - Address: 0x18, Default: NA
        26. 7.6.1.26 Register Name: config25 - Address: 0x19, Default: 0x0440
        27. 7.6.1.27 Register Name: config26 - Address: 0x1A, Default: 0x0020
        28. 7.6.1.28 Register Name: config27 - Address: 0x1B, Default: 0x0000
        29. 7.6.1.29 Register Name: config28 - Address: 0x1C, Default: 0x0000
        30. 7.6.1.30 Register Name: config29 - Address: 0x1D, Default: 0x0000
        31. 7.6.1.31 Register Name: config30 - Address: 0x1E, Default: 0x1111
        32. 7.6.1.32 Register Name: config31 - Address: 0x1F, Default: 0x1140
        33. 7.6.1.33 Register Name: config32 - Address: 0x20, Default: 0x2400
        34. 7.6.1.34 Register Name: config33 - Address: 0x21, Default: 0x0000
        35. 7.6.1.35 Register Name: config34 - Address: 0x22, Default: 0x1B1B
        36. 7.6.1.36 Register Name: config35 - Address: 0x23, Default: 0xFFFF
        37. 7.6.1.37 Register Name: config36 - Address: 0x24, Default: 0x0000
        38. 7.6.1.38 Register Name: config37 - Address: 0x25, Default: 0x7A7A
        39. 7.6.1.39 Register Name: config38 - Address: 0x26, Default: 0xB6B6
        40. 7.6.1.40 Register Name: config39 - Address: 0x27, Default: 0xEAEA
        41. 7.6.1.41 Register Name: config40 - Address: 0x28, Default: 0x4545
        42. 7.6.1.42 Register Name: config41 - Address: 0x29, Default: 0x1A1A
        43. 7.6.1.43 Register Name: config42 - Address: 0x2A, Default: 0x1616
        44. 7.6.1.44 Register Name: config43 - Address: 0x2B, Default: 0xAAAA
        45. 7.6.1.45 Register Name: config44 - Address: 0x2C, Default: 0xC6C6
        46. 7.6.1.46 Register Name: config45 - Address: 0x2D, Default: 0x0004
        47. 7.6.1.47 Register Name: config46 - Address: 0x2E, Default: 0x0000
        48. 7.6.1.48 Register Name: config47 - Address: 0x2F, Default: 0x0000
        49. 7.6.1.49 Register Name: config48 - Address: 0x30, Default: 0x0000
        50. 7.6.1.50 Register Name: version- Address: 0x7F, Default: 0x540C (READ ONLY)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 IF Based LTE Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Data Input Rate
          2. 8.2.1.2.2 Interpolation
          3. 8.2.1.2.3 LO Feedthrough and Sideband Correction
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Direct Upconversion (Zero IF) LTE Transmitter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Data Input Rate
          2. 8.2.2.2.2 Interpolation
          3. 8.2.2.2.3 LO Feedthrough and Sideband Correction
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Assembly
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Definition of Specifications
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DAC3482 is a dual 16-bit DAC with max input data rate of up to 625 MSPS per DAC and max DAC update rate of 1.25 GSPS after the final, selectable interpolation stages. With build-in interpolation filter of 2x, 4x, 8x, and 16x options, the lower input data rate can be interpolated all the way to 1.25 GSPS. This allows the DAC to update the samples at higher rate, and pushes the DAC images further away to relax anti-image filer specification due to the increased Nyquist bandwidth. With integrated coarse and fine mixers, baseband signal can be upconverted to an intermediate frequency (IF) signal between the baseband processor and post-DAC analog signal chains.

The DAC can output baseband or IF when connected to post-DAC analog signals chain components such as transformers or IF amplifiers. When used in conjunction with TI RF quadrature modulator such as the TRF3705, the DAC and RF modulator can function as a set of baseband or IF upconverter. With integrated QMC circuits, the LO offset and the sideband artifacts can be properly corrected in the direct up-conversion applications. The DAC3482 provides the bandwidth, performance, small footprint, and lower power consumption needed for multi-mode 2G/3G/4G cellular base stations to migrate to more advanced technologies, such as LTE-Advanced and carrier aggregation on multiple antennas.

8.2 Typical Applications

8.2.1 IF Based LTE Transmitter

Figure 91 shows an example block diagram for a direct conversion radio. The design requires a single carrier, 20-MHz LTE signal. The system has digital-predication (DPD) to correct up to 5th order distortion so the total DAC output bandwidth is 100 MHz. Interpolation is used to output the signal at highest sampling rate possible to simplify the analog filter requirements and move high order harmonics out of band (due to wider Nyquist zone). The internal PLL is used to generate the final DAC output clock from a reference clock of 491.52 MHz.

DAC3482 Dual_LTE_Trans_las748.gifFigure 91. Dual Low-IF Wideband LTE Transmitter Diagram

8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 11 as the input parameters.

Table 11. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Signal Bandwidth (BWsignal) 20 MHz
Total DAC Output Bandwidth (BWtotal) 100 MHz
DAC PLL Off
DAC PLL Reference Frequency 491.52 MHz
Maximum FPGA LVDS Rate 491.52 Mbps

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Data Input Rate

Nyquist theory states that the data rate must be at least two times the highest signal frequency. The data will be sent to the DAC as complex baseband data. Due to the quadrature nature of the signal, each in-phase (I component) and quadrature (Q component) need to have 50 MHz of bandwidth to construct 100 MHz of complex bandwidth. Since the interpolation filter design is not the ideal half-band filter design with infinite roll-off at FDATA/2 (refer to FIR Filters section for more detail), the filter limits the useable input bandwidth to about 40 percent of FDATA. Therefore, the minimum data input rate is 125 MSPS. Since the standard telecom data rate is typically multiples of 30.72 MSPS, the DAC input data rate is chosen to be eight times of 30.72 MSPS, which is 245.76 MSPS.

8.2.1.2.2 Interpolation

It is desired to use the highest DAC output rate as possible to move the DAC images further from the signal of interest to ease analog filter requirement. The DAC output rate must be greater than two times the highest output frequency of 200 MHz, which is greater than 400 MHz. Table 12 shows the possible DAC output rates based on the data input rate and available interpolation settings. The DAC image frequency is also listed.

Table 12. Interpolation

FDATA INTERPOLATION FDAC POSSIBLE? LOWEST IMAGE FREQUENCY DISTANCE FROM BAND OF INTEREST
245.76 MSPS 1 245.76 MSPS No N/A N/A
245.76 MSPS 2 491.52 MSPS Yes 318.64 MHz 145.76 MHz
245.76 MSPS 4 983.04 MSPS Yes 810.16 MHz 637.28 MHz
245.76 MSPS 8 1966.08 MSPS No N/A N/A
245.76 MSPS 16 3932.16 MSPS No N/A N/A

8.2.1.2.3 LO Feedthrough and Sideband Correction

For typical IF based systems, the IF location is selected such that the image location and the LO feedthrough location is far from the signal location. The minimum distance is based on the bandpass filter roll-off and attenuation level at the LO feedthrough and image location. If sufficient attenuation level of these two artifacts meets the system requirement, then further digital cancellation of these artifacts may not be needed.

Although the I/Q modulation process will inherently reduce the level of the RF sideband signal, an IF based transmitter without sufficient RF image rejection capabilities or an zero-IF based system (detail in the next section) will likely need additional sideband suppression to maximize performance. Further, any mixing process will result in some feedthrough of the LO source. The DAC3482 has build-in digital features to cancel both the LO feedthrough and sideband signal. The LO feedthrough is corrected by adding a DC offset to the DAC outputs until the LO feedthrough power is suppressed. The sideband suppression can be improved by correcting the gain and phase differences between the I and Q analog outputs through the digital QMC block. Besides gain and phase differences between the I and Q analog outputs, group delay differences may also be present in the signal path and are typically contributed by group delay variations of post DAC image reject analog filters and PCB trace variations. Since delay in time translates to higher order linear phase variation, the sideband of a wideband system may not be completely suppressed by typical digital QMC block. The DAC3482 has integrated group delay correction feature to provide delay adjustments. (The maximum group delay correction ranges from 30 ps to 100 ps and is dependent on DAC sample clock. Contact TI for specific application information.) Moreover, system designer may implement additional linear group delay compensation in the host processor to the DAC to perform higher order sideband suppression.

8.2.1.3 Application Curves

The ACPR performance for LTE 20 MHz TM1.1 are shown in Figure 92, Figure 93, Figure 93, and Figure 93. The figures provide comparisons between two major LTE bands such as 2.14 GHz and 2.655 GHz, and also comparisons between two different DAC clocking options such as DAC on-chip PLL mode and external clocking mode.

DAC3482 App_curve1_las748.png
DAC Output IF = 122.88 MHz, LO = 2017.12 MHz, DAC Clock = External Clock Source from LMK04806
Figure 92. 20MHz TM1.1 LTE Carrier at 2.14GHz
DAC3482 App_curve3_las748.png
DAC Output IF = 122.88 MHz, LO = 2532.12 MHz, DAC Clock = External Clock Source from LMK04806
Figure 94. 20MHz TM1.1 LTE Carrier at 2.655GHz
DAC3482 App_curve2_las748.png
DAC Output IF = 122.88 MHz, LO = 2017.12 MHz, DAC Clock = DAC3482 On-Chip PLL
Figure 93. 20MHz TM1.1 LTE Carrier at 2.14GHz
DAC3482 App_curve4_las748.png
DAC Output IF = 122.88 MHz, LO = 2532.12 MHz, DAC Clock = DAC3482 On-Chip PLL
Figure 95. 20MHz TM1.1 LTE Carrier at 2.655GHz

8.2.2 Direct Upconversion (Zero IF) LTE Transmitter

Figure 91 shows an example block diagram for a direct conversion radio. The design specification requires that the desired output bandwidth is 100MHz, which could be, for instance, a typical LTE signal. The system has DPD to correct up to 5th order distortion so the total DAC output bandwidth is 500 MHz. Interpolation is used to output the signal at the highest sampling rate possible to simplify the analog filtering requirements and move high order harmonics out of band (due to wider Nyquist zone). The DAC sampling clock is provided by high quality clock synthesizer such as the LMK0480x family.

DAC3482 Dual_Zero_Trans_las748.gifFigure 96. Zero LTE Transmitter Diagram

8.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 13 as the input parameters.

Table 13. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Signal Bandwidth (BWsignal) 100 MHz
Total DAC Output Bandwidth (BWtotal) 500 MHz
DAC PLL Off
Maximum FPGA LVDS Rate 1228.8 Mbps

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Data Input Rate

Nyquist theory states that the data rate must be at least two times the highest signal frequency. The data will be sent to the DAC as complex baseband data. Due to the quadrature nature of the signal, each in-phase (I component) and quadrature (Q component) need to have 250 MHz of bandwidth to construct 500 MHz of complex bandwidth. Since the interpolation filter design is not the ideal half-band filter design with infinite roll-off at FDATA/2 (refer to FIR Filters section for more detail), the filter limits the useable input bandwidth to about 44 percent of FDATA with less than 0.1dB of FIR filter roll-off. Therefore, the minimum data input rate is 568 MSPS. Since the standard telecom data rate is typically multiples of 30.72 MSPS, the DAC input data rate is chosen to be 20 times of 30.72 MSPS, which is 614.4 MSPS.

8.2.2.2.2 Interpolation

It is desired to use the highest DAC output rate as possible to move the DAC images further from the signal of interest to ease analog filter requirement. The DAC output rate must be greater than two times the highest output frequency of 250 MHz, which is greater than 500 MHz. The table below shows the possible DAC output rates based on the data input rate and available interpolation settings. The DAC image frequency is also listed.

Table 14. Interpolation

FDATA INTERPOLATION FDAC POSSIBLE? LOWEST IMAGE FREQUENCY DISTANCE FROM BAND OF INTEREST
614.4 MSPS 1 614.4 MSPS Yes 364.4 MHz 114.4 MHz
614.4 MSPS 2 1228.8 MSPS Yes 978.8 MHz 728.8 MHz
614.4 MSPS 4 2457.6 MSPS No N/A N/A
614.4 MSPS 8 4915.2 MSPS No N/A N/A
614.4 MSPS 16 9830.4 MSPS No N/A N/A

8.2.2.2.3 LO Feedthrough and Sideband Correction

Refer to LO Feedthrough and Sideband Correction section of IF based LTE Transmitter design.

8.2.2.3 Application Curves

The ACPR performance for LTE 20MHz TM1.1 are shown in Figure 97 and Figure 98. The figures provide comparisons between two major LTE bands such as 2.14 GHz and 2.655 GHz with DAC clocking option set to external clocking mode.

DAC3482 App_curve5_las748.png
DAC Output IF = 0 MHz, LO = 2140 MHz, DAC Clock = External Clock Source from LMK04806
Figure 97. 5x20MHz TM1.1 LTE Carrier at 2.14GHz
DAC3482 App_curve6_las748.png
DAC Output IF = 0 MHz, LO = 2655 MHz, DAC Clock = External Clock Source from LMK04806
Figure 98. 5x20MHz TM1.1 LTE Carrier at 2.655GHz