SLAS748F March   2011  – August 2015 DAC3482

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Digital Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Electrical Characteristics - Phase-Locked Loop Specifications
    9. 6.9  Timing Requirements - Digital Specifications
    10. 6.10 Switching Characteristics - AC Specifications
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Serial Interface
      2. 7.3.2  Data Interface
        1. 7.3.2.1 Word-Wide Format
        2. 7.3.2.2 Byte-Wide Format
      3. 7.3.3  Input FIFO
      4. 7.3.4  FIFO Modes of Operation
        1. 7.3.4.1 Dual Sync Source Mode
        2. 7.3.4.2 Single Sync Source Mode
        3. 7.3.4.3 Bypass Mode
      5. 7.3.5  Clocking Modes
        1. 7.3.5.1 PLL Bypass Mode
        2. 7.3.5.2 PLL Mode
      6. 7.3.6  FIR Filters
      7. 7.3.7  Complex Signal Mixer
        1. 7.3.7.1 Full Complex Mixer
        2. 7.3.7.2 Coarse Complex Mixer
        3. 7.3.7.3 Mixer Gain
        4. 7.3.7.4 Real Channel Upconversion
      8. 7.3.8  Quadrature Modulation Correction (QMC)
        1. 7.3.8.1 Gain and Phase Correction
        2. 7.3.8.2 Offset Correction
        3. 7.3.8.3 Group Delay Correction
      9. 7.3.9  Temperature Sensor
      10. 7.3.10 Data Pattern Checker
      11. 7.3.11 Parity Check Test
        1. 7.3.11.1 Word-by-Word Parity
        2. 7.3.11.2 Block Parity
      12. 7.3.12 DAC3482 Alarm Monitoring
      13. 7.3.13 LVPECL Inputs
      14. 7.3.14 LVDS Inputs
      15. 7.3.15 Unused LVDS Port Termination
      16. 7.3.16 CMOS Digital Inputs
      17. 7.3.17 Reference Operation
      18. 7.3.18 DAC Transfer Function
      19. 7.3.19 Analog Current Outputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Multi-Device Synchronization
        1. 7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
        2. 7.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
        3. 7.4.1.3 Multi-Device Operation: Single Sync Source Mode
    5. 7.5 Programming
      1. 7.5.1 Power-Up Sequence
      2. 7.5.2 Example Start-Up Routine
        1. 7.5.2.1 Device Configuration
        2. 7.5.2.2 PLL Configuration
        3. 7.5.2.3 NCO Configuration
        4. 7.5.2.4 Example Start-Up Sequence
    6. 7.6 Register Map
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  Register Name: config0 - Address: 0x00, Default: 0x049C
        2. 7.6.1.2  Register Name: config1 - Address: 0x01, Default: 0x050E
        3. 7.6.1.3  Register Name: config2 - Address: 0x02, Default: 0x7000
        4. 7.6.1.4  Register Name: config3 - Address: 0x03, Default: 0xF000
        5. 7.6.1.5  Register Name: config4 - Address: 0x04, Default: No RESET Value (WRITE TO CLEAR)
        6. 7.6.1.6  Register Name: config5 - Address: 0x05, Default: Setup and Power-Up Conditions Dependent (WRITE TO CLEAR)
        7. 7.6.1.7  Register Name: config6 - Address: 0x06, Default: No RESET Value (READ ONLY)
        8. 7.6.1.8  Register Name: config7 - Address: 0x07, Default: 0xFFFF
        9. 7.6.1.9  Register Name: config8 - Address: 0x08, Default: 0x0000 (CAUSES AUTO-SYNC)
        10. 7.6.1.10 Register Name: config9 - Address: 0x09, Default: 0x8000
        11. 7.6.1.11 Register Name: config10 - Address: 0x0A, Default: 0x0000
        12. 7.6.1.12 Register Name: config11 - Address: 0x0B, Default: 0x0000
        13. 7.6.1.13 Register Name: config12 - Address: 0x0C, Default: 0x0400
        14. 7.6.1.14 Register Name: config13 - Address: 0x0D, Default: 0x0400
        15. 7.6.1.15 Register Name: config14 - Address: 0x0E, Default: 0x0400
        16. 7.6.1.16 Register Name: config15 - Address: 0x0F, Default: 0x0400
        17. 7.6.1.17 Register Name: config16 - Address: 0x10, Default: 0x0000 (CAUSES AUTO-SYNC)
        18. 7.6.1.18 Register Name: config17 - Address: 0x11, Default: 0x0000
        19. 7.6.1.19 Register Name: config18 - Address: 0x12, Default: 0x0000 (CAUSES AUTO-SYNC)
        20. 7.6.1.20 Register Name: config19 - Address: 0x13, Default: 0x0000
        21. 7.6.1.21 Register Name: config20 - Address: 0x14, Default: 0x0000
        22. 7.6.1.22 Register Name: config21 - Address: 0x15, Default: 0x0000
        23. 7.6.1.23 Register name: config22 - Address: 0x16, Default: 0x0000
        24. 7.6.1.24 Register Name: config23 - Address: 0x17, Default: 0x0000
        25. 7.6.1.25 Register Name: config24 - Address: 0x18, Default: NA
        26. 7.6.1.26 Register Name: config25 - Address: 0x19, Default: 0x0440
        27. 7.6.1.27 Register Name: config26 - Address: 0x1A, Default: 0x0020
        28. 7.6.1.28 Register Name: config27 - Address: 0x1B, Default: 0x0000
        29. 7.6.1.29 Register Name: config28 - Address: 0x1C, Default: 0x0000
        30. 7.6.1.30 Register Name: config29 - Address: 0x1D, Default: 0x0000
        31. 7.6.1.31 Register Name: config30 - Address: 0x1E, Default: 0x1111
        32. 7.6.1.32 Register Name: config31 - Address: 0x1F, Default: 0x1140
        33. 7.6.1.33 Register Name: config32 - Address: 0x20, Default: 0x2400
        34. 7.6.1.34 Register Name: config33 - Address: 0x21, Default: 0x0000
        35. 7.6.1.35 Register Name: config34 - Address: 0x22, Default: 0x1B1B
        36. 7.6.1.36 Register Name: config35 - Address: 0x23, Default: 0xFFFF
        37. 7.6.1.37 Register Name: config36 - Address: 0x24, Default: 0x0000
        38. 7.6.1.38 Register Name: config37 - Address: 0x25, Default: 0x7A7A
        39. 7.6.1.39 Register Name: config38 - Address: 0x26, Default: 0xB6B6
        40. 7.6.1.40 Register Name: config39 - Address: 0x27, Default: 0xEAEA
        41. 7.6.1.41 Register Name: config40 - Address: 0x28, Default: 0x4545
        42. 7.6.1.42 Register Name: config41 - Address: 0x29, Default: 0x1A1A
        43. 7.6.1.43 Register Name: config42 - Address: 0x2A, Default: 0x1616
        44. 7.6.1.44 Register Name: config43 - Address: 0x2B, Default: 0xAAAA
        45. 7.6.1.45 Register Name: config44 - Address: 0x2C, Default: 0xC6C6
        46. 7.6.1.46 Register Name: config45 - Address: 0x2D, Default: 0x0004
        47. 7.6.1.47 Register Name: config46 - Address: 0x2E, Default: 0x0000
        48. 7.6.1.48 Register Name: config47 - Address: 0x2F, Default: 0x0000
        49. 7.6.1.49 Register Name: config48 - Address: 0x30, Default: 0x0000
        50. 7.6.1.50 Register Name: version- Address: 0x7F, Default: 0x540C (READ ONLY)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 IF Based LTE Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Data Input Rate
          2. 8.2.1.2.2 Interpolation
          3. 8.2.1.2.3 LO Feedthrough and Sideband Correction
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Direct Upconversion (Zero IF) LTE Transmitter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Data Input Rate
          2. 8.2.2.2.2 Interpolation
          3. 8.2.2.2.3 LO Feedthrough and Sideband Correction
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Assembly
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Definition of Specifications
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage(2) DACVDD, DIGVDD, CLKVDD –0.5 1.5 V
VFUSE –0.5 1.5 V
IOVDD –0.5 4 V
AVDD, PLLAVDD –0.5 4 V
Pin voltage(2) D[15..0]P/N, DATACLKP/N, FRAMEP/N, PARITYP/N, SYNCP/N –0.5 IOVDD + 0.5 V
DACCLKP/N, OSTRP/N –0.5 CLKVDD + 0.5 V
ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TESTMODE, TXENABLE –0.5 IOVDD + 0.5 V
IOUTIP/N, IOUTQP/N –1.0 AVDD + 0.5 V
EXTIO, BIASJ –0.5 AVDD + 0.5 V
LPF 0.5 PLLAVDD + 0.5V V
Peak input current (any input) 20 mA
Peak total input current (all inputs) –30 mA
Operating free-air temperature, TA –40 85 °C
Absolute maximum junction temperature, TJ 150 °C
Storage temperature, TSTG –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to GND.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
TJ Recommended operating junction temperature 105 °C
Maximum rated operating junction temperature(1) 125
TA Recommended free-air temperature –40 25 85 °C
(1) Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.

6.4 Thermal Information

THERMAL METRIC(1) DAC3482 UNIT
RKD PACKAGE (WQFN-MR) ZAY PACKAGE (NFBGA)
88 PIN 196 BALL
RθJA Junction-to-ambient thermal resistance 22.1 37.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 7.1 6.8 °C/W
RθJB Junction-to-board thermal resistance 4.7 16.8 °C/W
ψJT Junction-to-top characterization parameter 0.1 0.2 °C/W
ψJB Junction-to-board characterization parameter 4.6 16.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.6 N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics – DC Specifications

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 16 Bits
DC ACCURACY
DNL Differential nonlinearity 1 LSB = IOUTFS/216 ±2 LSB
INL Integral nonlinearity ±4 LSB
ANALOG OUTPUT
Coarse gain linearity ±0.04 LSB
Offset error Mid code offset ±0.001 %FSR
Gain error With external reference ±2 %FSR
With internal reference ±2 %FSR
Gain mismatch With internal reference ±2 %FSR
Full scale output current 10 20 30 mA
Output compliance range –0.5 0.6 V
Output resistance 300
Output capacitance 5 pF
REFERENCE OUTPUT
VREF Reference output voltage 1.2 V
Reference output current(2) 100 nA
REFERENCE INPUT
VEXTIO Input voltage range External Reference Mode 0.6 1.2 1.25 V
Input resistance 1
Small signal bandwidth 472 kHz
Input capacitance 100 pF
TEMPERATURE COEFFICIENTS
Offset drift ±1 ppm/°C
Gain drift With external reference ±15 ppm/°C
With internal reference ±30 ppm/°C
Reference voltage drift ±8 ppm/°C
POWER SUPPLY(4)
AVDD, IOVDD, PLLAVDD All conditions 3.14 3.3 3.46 V
DIGVDD All conditions 1.14 1.2 1.32 V
CLKVDD, DACVDD(5) FDAC Sample Rate ≤ 1.25 GSPS, PLL OFF 1.14 1.2 1.32 V
FDAC Sample Rate ≤ 1 GSPS, PLL ON 1.14 1.2 1.32
FDAC Sample Rate ≥ 1 GSPS, PLL ON 1.25 1.29 1.32
PSRR Power supply rejection ratio DC tested ±0.2 %FSR/V
POWER CONSUMPTION
I(AVDD) Analog supply current(3) MODE 1
fDAC = 1.25 GSPS, 2x interpolation, Mixer on,
QMC on, invsinc on,
PLL enabled, 20-mA FS output, IF = 200 MHz
80 85 mA
I(DIGVDD) Digital supply current 390 450 mA
I(DACVDD) DAC supply current 30 50 mA
I(CLKVDD) Clock supply current 95 110 mA
P Power dissipation 882 980 mW
I(AVDD) Analog supply current(3) MODE 2
fDAC = 1.25 GSPS, 2x interpolation, Mixer on,
QMC on, invsinc on,
PLL disabled, 20-mA FS output, IF = 200 MHz
65 mA
I(DIGVDD) Digital supply current 385 mA
I(DACVDD) DAC supply current 30 mA
I(CLKVDD) Clock supply current 70 mA
P Power dissipation 800 mW
I(AVDD) Analog supply current(3) MODE 3
fDAC = 625 MSPS, 2x interpolation, Mixer on,
QMC on, invsinc off,
PLL disabled, 20-mA FS output, IF = 200 MHz
65 mA
I(DIGVDD) Digital supply current 190 mA
I(DACVDD) DAC supply current 15 mA
I(CLKVDD) Clock supply current 45 mA
P Power dissipation 515 mW
I(AVDD) Analog supply current(3) MODE 4
fDAC = 1.25 GSPS, 2x interpolation, Mixer on,
QMC on, invsinc on,
PLL enabled, I/Q output sleep, IF = 200 MHz,
35 mA
I(DIGVDD) Digital supply current 395 mA
I(DACVDD) DAC supply current 30 mA
I(CLKVDD) Clock supply current 95 mA
P Power dissipation 740 mW
I(AVDD) Analog supply current(3) Mode 5
Power-Down mode: No clock,
DAC on sleep mode (clock receiver sleep),
I/Q output sleep, static data pattern
20 mA
I(DIGVDD) Digital supply current 10 mA
I(DACVDD) DAC supply current 4 mA
I(CLKVDD) Clock supply current 10 mA
P Power dissipation 95 mW
I(AVDD) Analog supply current(4) Mode 6
fDAC = 1 GSPS, 2x interpolation, Mixer off,
QMC off, invsinc off, PLL enabled, 20-mA FS output, IF = 200 MHz
80 mA
I(DIGVDD) Digital supply current 200 mA
I(DACVDD) DAC supply current 25 mA
I(CLKVDD) Clock supply current 85 mA
P Power dissipation 636 mW
(1) Measured differentially across IOUTP/N with 25 Ω each to GND.
(2) Use an external buffer amplifier with high impedance input to drive any external load.
(3) Includes AVDD, PLLAVDD, and IOVDD.
(4) To ensure power supply accuracy and to account for power supply filter network loss at operating conditions, the use of the ATEST function in register config27 to check the internal power supply nodes is recommended.

6.6 Electrical Characteristics – Digital Specifications

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVDS INPUTS: D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N, PARITYP/N(1)
VA,B+ Logic high differential input voltage threshold 200 mV
VA,B– Logic low differential input voltage threshold –200 mV
VCOM Input common mode 1.0 1.2 1.6 V
ZT Internal termination 85 110 135 Ω
CL LVDS Input capacitance 2 pF
fINTERL Interleaved LVDS data transfer rate 1250 MSPS
fDATA Input data rate Word-wide interface mode 625 MSPS
Byte-wide interface mode 312.5
CLOCK INPUT (DACCLKP/N)
Differential voltage(2) |DACCLKP - DACCLKN| 0.4 0.8 V
Internally biased common-mode voltage 0.2 V
Single-ended input level(3) –0.4 V
OUTPUT STROBE (OSTRP/N)
Differential voltage |OSTRP – OSTRN| 0.4 0.8 V
Internally biased common-mode voltage 0.2 V
Single-ended input level(3) –0.4 V
CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENABLE
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IIH High-level input current -40 40 µA
IIL Low-level input current -40 40 µA
CI CMOS input capacitance 2 pF
VOH ALARM, SDO, SDIO Iload = –100 μA IOVDD – 0.2 V
Iload = –2 mA 0.8 x IOVDD V
VOL ALARM, SDO, SDIO Iload = 100 μA 0.2 V
Iload = 2 mA 0.5 V
(1) See LVDS Inputs section for terminology.
(2) Standard high swing LVPECL clock signal should be applied for best performance.
(3) Indicates the minimum voltage that can be applied to the DACCLK and OSTR differential pins in single-ended fashion.

6.7 Electrical Characteristics – AC Specifications

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG OUTPUT(1)
fDAC Maximum DAC rate(4) PLL OFF 1250 MSPS
PLL ON - devices without enhanced test coverage 1000
PLL ON - devices with enhanced test coverage 1250
AC PERFORMANCE(2)
SFDR Spurious free dynamic range (0 to fDAC/2) tone at 0 dBFS fDAC = 1.25 GSPS, fOUT = 20 MHz 82 dBc
fDAC = 1.25 GSPS, fOUT = 50 MHz 77
fDAC = 1.25 GSPS, fOUT = 70 MHz 72
IMD3 Third-order two-tone intermodulation distortion
Each tone at –12 dBFS
fDAC = 1.25 MSPS, fOUT = 30 ± 0.5 MHz 81 dBc
fDAC = 1.25 GSPS, fOUT = 50 ± 0.5 MHz 79
fDAC = 1.25 GSPS, fOUT = 100 ± 0.5 MHz 77.5
NSD Noise spectral density
Tone at 0dBFS
fDAC = 1.25 GSPS, fOUT = 10 MHz 160 dBc/Hz
fDAC = 1.25 GSPS, fOUT = 80 MHz 155
ACLR(3) Adjacent channel leakage ratio, single carrier fDAC = 1.2288 GSPS, fOUT = 30.72 MHz 77 dBc
fDAC = 1.2288 GSPS, fOUT = 153.6 MHz 74
Alternate channel leakage ratio, single carrier fDAC = 1.2288 GSPS, fOUT = 30.72 MHz 82
fDAC = 1.2288 GSPS, fOUT = 153.6 MHz 80
Channel isolation fDAC = 1.25 GSPS, fOUT = 10 MHz 84 dBc
(1) Measured single ended into 50-Ω load.
(2) 4:1 transformer output termination, 50-Ω doubly terminated load.
(3) Single carrier, W-CDMA with 3.84-MHz BW, 5-MHz spacing, centered at IF, PAR = 12dB. TESTMODEL 1, 10 ms

6.8 Electrical Characteristics - Phase-Locked Loop Specifications

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN(1) TYP(1) MAX(1) UNIT
Phase-locked loop CONFIG26, pll_vco(5:0) – binary value / decimal value b111111 / 63 3900 4000 MHz
b111010 / 58 3850 3950 MHz
b110110 / 54 3800 3900 MHz
b110010 / 50 3770 3840 MHz
b101110 / 46 3730 3790 MHz
b101010 / 42 3690 3750 MHz
b100110 / 38 3650 3700 MHz
b100010 / 34 3600 3650 MHz
b011110 / 30 3580 3600 MHz
b010111 / 23(2)
(1) On-chip VCO range
(2) Tested at 3500 MHz

6.9 Timing Requirements - Digital Specifications

MIN NOM MAX UNIT
CLOCK INPUT (DACCLKP/N)
Duty cycle 40% 60%
DACCLKP/N input frequency 1250 MHz
OUTPUT STROBE (OSTRP/N)
fOSTR Frequency fOSTR = fDACCLK / (n x 8 x Interp) where n is any positive integer, fDACCLK is DACCLK frequency in MHz fDACCLK /
(8 x interp)
MHz
Duty cycle 50%
DIGITAL INPUT TIMING SPECIFICATIONS
Timing LVDS inputs: D[15:0]P/N, FRAMEP/N, SYNCP/N, PARITYP/N, double edge latching
ts(DATA) Setup time, D[15:0]P/N, FRAMEP/N, SYNCP/N and PARITYP/N, valid to either edge of DATACLKP/N FRAMEP/N reset and frame indicator latched on rising edge of DATACLKP/N.
FRAMEP/N parity bit latched on falling edge of DATACLKP/N.
Config36 Setting
datadly clkdly
0 0 150 ps
0 1 100
0 2 50
0 3 0
0 4 -50
0 5 -100
0 6 -150
0 7 -200
1 0 200
2 0 250
3 0 300
4 0 350
5 0 400
6 0 450
7 0 500
th(DATA) Hold time, D[15:0]P/N, FRAMEP/N, SYNCP/N and PARITYP/N, valid after either edge of DATACLKP/N FRAMEP/N reset and frame indicator latched on rising edge of DATACLKP/N.
FRAMEP/N parity bit latched on falling edge of DATACLKP/N.
Config36 Setting ps
datadly clkdly
0 0 350
0 1 400
0 2 450
0 3 500
0 4 550
0 5 600
0 6 650
0 7 700
1 0 300
2 0 250
3 0 200
4 0 150
5 0 100
6 0 50
7 0 0
t(FRAME_SYNC) FRAMEP/N and SYNCP/N pulse width fDATACLK is DATACLK frequency in MHz 1/2fDATACLK ns
TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING(1)
ts(OSTR) Setup time, OSTRP/N valid to rising edge of DACCLKP/N 0 ps
th(OSTR) Hold time, OSTRP/N valid after rising edge of DACCLKP/N 300 ps
TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING(2)
ts(SYNC_PLL) Setup time, SYNCP/N valid to rising edge of DACCLKP/N 200 ps
th(SYNC_PLL) Hold time, SYNCP/N valid after rising edge of DACCLKP/N 300 ps
TIMING SERIAL PORT
ts(SDENB) Setup time, SDENB to rising edge of SCLK 20 ns
ts(SDIO) Setup time, SDIO valid to rising edge of SCLK 10 ns
th(SDIO) Hold time, SDIO valid to rising edge of SCLK 5 ns
t(SCLK) Period of SCLK Register config6 read (temperature sensor read) 1 µs
All other registers 100 ns
td(Data) Data output delay after falling edge of SCLK 10 ns
tRESET Minimum RESETB pulse width 25 ns
(1) OSTR is required in Dual Sync Sources mode. In order to minimize the skew it is recommended to use the same clock distribution device such as Texas Instruments CDCE62005 or LMK0480x family to provide the DACCLK and OSTR signals to all the DAC3482 devices in the system. Swap the polarity of the DACCLK outputs with respect to the OSTR ones to establish proper phase relationship.
(2) SYNC is required to synchronize the PLL circuit in multiple devices. The SYNC signal must meet the timing relationship with respect to the reference clock (DACCLKP/N) of the on-chip PLL circuit.

6.10 Switching Characteristics – AC Specifications

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG OUTPUT(1)
ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF 10 ns
tpd Output propagation delay DAC outputs are updated on the falling edge of DAC clock. Does not include Digital Latency (see below). 2 ns
tr(IOUT) Output rise time 10% to 90% 220 ps
tf(IOUT) Output fall time 90% to 10% 220 ps
Digital latency 8-bit
interface
No interpolation, FIFO enabled, Mixer off, QMC off, Inverse sinc off 250 DAC clock cycles
2x Interpolation 212
4x Interpolation 372
8x Interpolation 723
16x Interpolation 1440
16-bit
interface
No interpolation, FIFO enabled, Mixer off, QMC off, Inverse sinc off 140
2x Interpolation 228
4x Interpolation 417
8x Interpolation 817
16x Interpolation 1630
Fine mixer 24
QMC 32
Inverse sinc 36
Power-up
Time
DAC wake-up time IOUT current settling to 1% of IOUTFS from output sleep 2 µs
DAC sleep time IOUT current settling to less than 1% of IOUTFS in output sleep 2
(1) Measured single ended into 50-Ω load.

6.11 Typical Characteristics

All plots are at 25°C, nominal supply voltage, fDAC = 1250 MSPS, 4x interpolation, NCO enabled, Mixer Gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20-mA full-scale output current with 4:1 transformer (unless otherwise noted)
DAC3482 G001_LAS748.pngFigure 1. Integral Nonlinearity
DAC3482 G003_LAS748.pngFigure 3. SFDR vs Output Frequency Over Input Scale
DAC3482 G005_LAS748.pngFigure 5. Third Harmonic Distortion vs
Output Frequency Over Input Scale
DAC3482 G007_LAS748.pngFigure 7. SFDR vs Output Frequency Over fDAC
DAC3482 G009_LAS748.pngFigure 9. Single Tone Spectral Plot
DAC3482 G011_LAS748.pngFigure 11. Single Tone Spectral Plot
DAC3482 G013_LAS748.pngFigure 13. Single Tone Spectral Plot
DAC3482 G015_LAS748.pngFigure 15. IMD3 vs Output Frequency Over Interpolation
DAC3482 G017_LAS748.pngFigure 17. IMD3 vs Output Frequency Over IOUTFS
DAC3482 G019_LAS748.pngFigure 19. Two Tone Spectral Plot
DAC3482 G021_las748B.pngFigure 21. NSD vs Output Frequency Over Interpolation
DAC3482 G023_las748B.pngFigure 23. NSD vs Output Frequency Over IOUTFS
DAC3482 G025_LAS748.pngFigure 25. Single Carrier WCDMA ACLR (Adjacent) vs
Output Frequency Over Clocking Options
DAC3482 G027_LAS748.gifFigure 27. Single Carrier W-CDMA Test Model 1
DAC3482 G029_LAS748.gif
Figure 29. Single Carrier W-CDMA Test Model 1
DAC3482 G031_LAS748.gifFigure 31. Four Carrier W-CDMA Test Model 1
DAC3482 G033_LAS748.gifFigure 33. 10 MHz Single Carrier LTE Test Model 3.1
DAC3482 G035_LAS748.gifFigure 35. 20 MHz Single Carrier LTE Test Model 3.1
DAC3482 G037_LAS748.pngFigure 37. Power Consumption vs fDAC Over Interpolation
DAC3482 G039_LAS748.pngFigure 39. Power Consumption vs fDAC Over Digital
Processing Functions
DAC3482 G041_LAS748.pngFigure 41. DIGVDD Current vs fDAC Over Interpolation
DAC3482 G043_LAS748.pngFigure 43. DACVDD Current vs fDAC
DAC3482 G045_LAS748.pngFigure 45. AVDD Current vs fDAC
DAC3482 G048_des_las748c.gifFigure 47. SFDR vs Output Frequency
DAC3482 G002_LAS748.pngFigure 2. Differential Nonlinearity
DAC3482 G004_LAS748.pngFigure 4. Second Harmonic Distortion vs
Output Frequency Over Input Scale
DAC3482 G006_LAS748.pngFigure 6. SFDR vs Output Frequency Over Interpolation
DAC3482 G008_LAS748.pngFigure 8. SFDR vs Output Frequency Over IOUTFS
DAC3482 G010_LAS748.pngFigure 10. Single Tone Spectral Plot
DAC3482 G012_LAS748.pngFigure 12. Single Tone Spectral Plot
DAC3482 G014_LAS748.pngFigure 14. IMD3 vs Output Frequency Over Input Scale
DAC3482 G016_LAS748.pngFigure 16. IMD3 vs Output Frequency Over fDAC
DAC3482 G018_LAS748.pngFigure 18. Two Tone Spectral Plot
DAC3482 G020_las748B.pngFigure 20. NSD vs Output Frequency Over Input Scale
DAC3482 G022_las748B.pngFigure 22. NSD vs Output Frequency Over fDAC
DAC3482 G024_LAS748.pngFigure 24. NSD vs Output Frequency Over Clocking Options
DAC3482 G026_LAS748.pngFigure 26. Single Carrier WCDMA ACLR (Alternate) vs
Output Frequency Over Clocking Options
DAC3482 G028_LAS748.gifFigure 28. Single Carrier W-CDMA Test Model 1
DAC3482 G030_LAS748.gifFigure 30. Four Carrier W-CDMA Test Model 1
DAC3482 G032_LAS748.gifFigure 32. Four Carrier W-CDMA Test Model 1
DAC3482 G034_LAS748.gifFigure 34. 10 MHz Single Carrier LTE Test Model 3.1
DAC3482 G036_LAS748.gifFigure 36. 20 MHz Single Carrier LTE Test Model 3.1
DAC3482 G038_LAS748.pngFigure 38. Power Consumption vs fDAC Over Interpolation
DAC3482 G040_LAS748.pngFigure 40. DIGVDD Current vs fDAC Over Interpolation
DAC3482 G042_LAS748.pngFigure 42. DIGVDD Current vs fDAC Over Digital
Processing Functions
DAC3482 G044_LAS748.pngFigure 44. CLKVDD Current vs fDAC
DAC3482 G046_LAS748.pngFigure 46. Isolation Level vs Output Frequency
DAC3482 G049_des_las748c.gifFigure 48. IMD3 vs Output Frequency