The update mode for each DAC channel is determined by the status of its corresponding SYNC-EN bit. In asynchronous mode, a write to the DAC data register results in an immediate update of the DAC active register and DAC output on CS rising edge. In synchronous mode, writing to the DAC data register does not automatically update the DAC output. Instead the update occurs only after an LDAC trigger event. An LDAC trigger is generated through the LDAC bit in the TRIGGER register. The synchronous update mode enables simultaneous update of multiple DAC outputs. In both update modes a minimum wait time of 1 µs is required between DAC output updates.