SBAS856D June   2017  – May 2019 DAC8740H , DAC8741H

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: DAC8740H
    2.     Pin Functions: DAC8741H
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  HART Modulator
      2. 8.3.2  HART Demodulator
      3. 8.3.3  FOUNDATION Fieldbus or PROFIBUS PA Manchester Encoder
      4. 8.3.4  FOUNDATION Fieldbus or PROFIBUS PA Manchester Decoder
      5. 8.3.5  Internal Reference
      6. 8.3.6  Clock Configuration
      7. 8.3.7  Reset and Power-Down
      8. 8.3.8  Full-Duplex Mode
      9. 8.3.9  I/O Selection
      10. 8.3.10 Jabber Inhibitor
    4. 8.4 Device Functional Modes
      1. 8.4.1 UART Interfaced HART
      2. 8.4.2 UART Interfaced FOUNDATION Fieldbus or PROFIBUS PA
      3. 8.4.3 SPI Interfaced HART
      4. 8.4.4 SPI Interfaced FOUNDATION Fieldbus or PROFIBUS PA
      5. 8.4.5 Digital Interface
        1. 8.4.5.1 UART
          1. 8.4.5.1.1 UART Carrier Detect
        2. 8.4.5.2 SPI
          1. 8.4.5.2.1 SPI Cyclic Redundancy Check
          2. 8.4.5.2.2 SPI Interrupt Request
    5. 8.5 Register Maps
      1. 8.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
        1. Table 9. CONTROL Register Field Descriptions
      2. 8.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
        1. Table 10. RESET Register Field Descriptions
      3. 8.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
        1. Table 11. MODEM_STATUS Register Field Descriptions
      4. 8.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
        1. Table 12. MODEM_IRQ_MASK Register Field Descriptions
      5. 8.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
        1. Table 13. MODEM_CONTROL Register Field Descriptions
      6. 8.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
        1. Table 14. FIFO_D2M Register Field Descriptions
      7. 8.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
        1. Table 15. FIFO_M2D Register Field Descriptions
      8. 8.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
        1. Table 16. FIFO_LEVEL_SET Register Field Descriptions
      9. 8.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
        1. Table 17. PAFF_JABBER Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design Recommendations
      2. 9.1.2 Selecting the Crystal or Resonator
      3. 9.1.3 Included Functions and Filter Selection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DAC8740H HART Modem
        2. 9.2.2.2 2-Wire Current Loop
        3. 9.2.2.3 Regulator
        4. 9.2.2.4 DAC
        5. 9.2.2.5 Amplifiers
        6. 9.2.2.6 Diodes
        7. 9.2.2.7 Passives
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]

The modem status register is a read/write register. When an event occurs, the corresponding bit to indicate that event is set to a logic 1 in this register. The status bits are sticky, meaning they are not cleared unless a 1 is written to the corresponding bit position, except for carrier detect, or CD, which responds based on the presences of a carrier, the FIFO level registers, which respond based on the conditions of the FIFOs, and JAB_OFF and JAB_ON which represent the current status of the jabber inibhior. CTS will assert after RTS is set and no carrier is present if not operating in full-duplex mode.

MODEM_STATUS is shown in Figure 25 and described in Table 11.

Return to Summary Table.

Figure 25. MODEM_STATUS Register
15 14 13 12 11 10 9 8
RST JAB_OFF JAB_ON GAP FRAME PARITY WDT CRC
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
FIFO_M2D LEVEL FIFO_M2D FULL FIFO_M2D EMPTY FIFO_D2M LEVEL FIFO_D2M FULL FIFO_D2M EMPTY CD CTS
R/W R/W R/W R/W R/W R/W R R

Table 11. MODEM_STATUS Register Field Descriptions

Bit Field Type Reset Description
15 RST R/W 0 A reset has occurred
14 JAB_OFF R/W 0 This bit goes high when the jabber inhibitor timeout period has expired
13 JAB_ON R/W 0 This bit goes high when the jabber inhibitor has been triggered
12 GAP R/W 0 A gap error in HART mode
11 FRAME R/W 0 A frame error in HART mode or a 1/2-bit slip in FF/PA mode
10 PARITY R/W 0 A Parity error in HART mode
9 WDT R/W 0 The watchdog timer has expired
8 CRC R/W 0 An incorrect CRC word was provided in a read or write command
7 FIFO_M2D_LEVEL R/W 0 The receive FIFO is at the programmed level
6 FIFO_M2D_FULL R/W 0 The receive FIFO is full
5 FIFO_M2D_EMPTY R/W 0 The receive FIFO is empty
4 FIFO_D2M_LEVEL R/W 0 The transmit FIFO is at the programmed level
3 FIFO_D2M_FULL R/W 0 The transmit FIFO is full
2 FIFO_D2M_EMPTY R/W 0 The transmit FIFO is empty
1 CD R 0 In HART mode, a valid carrier has been detected
0 CTS R 0 In HART mode, the modem is cleared to send data and the modulator is active