SBAS538D December   2013  – December 2021 DAC7750 , DAC8750

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: AC
    7. 7.7  Timing Requirements: Write Mode
    8. 7.8  Timing Requirements: Readback Mode
    9. 7.9  Timing Diagrams
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DAC Architecture
      2. 8.3.2  Current Output Stage
      3. 8.3.3  Internal Reference
      4. 8.3.4  Digital Power Supply
      5. 8.3.5  DAC Clear
      6. 8.3.6  Power-On Reset
      7. 8.3.7  Alarm Detection
      8. 8.3.8  Watchdog Timer
      9. 8.3.9  Frame Error Checking
      10. 8.3.10 User Calibration
      11. 8.3.11 Programmable Slew Rate
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Current-Output Ranges
      2. 8.4.2 Current-Setting Resistor
      3. 8.4.3 BOOST Configuration for IOUT
      4. 8.4.4 Filtering The Current Output
      5. 8.4.5 Output Current Monitoring
      6. 8.4.6 HART Interface
        1. 8.4.6.1 Implementing HART in 4-mA to 20-mA Mode
        2. 8.4.6.2 Implementing HART in All Current Output Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 SPI Shift Register
        2. 8.5.1.2 Write Operation
        3. 8.5.1.3 Read Operation
        4. 8.5.1.4 Stand-Alone Operation
        5. 8.5.1.5 Multiple Devices on the Bus
    6. 8.6 Register Maps
      1. 8.6.1 DACx750 Register Descriptions
        1. 8.6.1.1 Control Register
        2. 8.6.1.2 Configuration Register
        3. 8.6.1.3 DAC Registers
        4. 8.6.1.4 Reset Register
        5. 8.6.1.5 Status Register
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 HART Implementation
        1. 9.1.1.1 Using the CAP2 Pin
        2. 9.1.1.2 Using the ISET-R Pin
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

User Calibration

The device implements a user-calibration function (enabled by the CALEN bit in the Configuration Register) to trim system gain and zero errors. The DAC output is calibrated according to the value of the gain calibration and zero calibration registers. The range of gain adjustment is typically ±50% of full-scale with 1 LSB per step. The gain register must be programmed to 0x8000 to achieve the default gain of 1 because the power-on value of the register is 0x0000, equivalent to a gain of 0.5. The zero code adjustment is typically ±32,768 LSBs with 1 LSB per step. The input data format of the gain register is unsigned straight binary, and the input data format of the zero register is 2's complement. The gain and offset calibration is described by Equation 4.

Equation 4. GUID-288B49E1-B170-41E5-9DAB-C74D707274FC-low.gif

where

  • CODE is the decimal equivalent of the code loaded to the DAC data register at address 0x01
  • N is the bits of resolution (16 for DAC8750 and 12 for DAC7750)
  • User_ZERO is the signed 16-bit code in the zero register
  • User_GAIN is the unsigned 16-bit code in the gain register
  • CODE_OUT is the decimal equivalent of the code loaded to the DAC (limited between 0x0000 to 0xFFFF for DAC8750 and 0x000 to 0xFFF for DAC7750)

This is a purely digital implementation and the output is still limited by the programmed value at both ends of the current output range (set by the RANGE bits, as described in Section 8.4.1). In addition, the correction only makes sense for endpoints inside of the true device end points. To correct more than just the actual device error (for example, a system offset), the valid range for the adjustment changes accordingly and must be taken into account.

New calibration codes are only applied to subsequent writes to the DAC data register. Updating the calibration codes does not automatically update the DAC output. Additionally, before applying new DAC data, configure the calibration codes along with the slew rate control.