SLVSBY7 February 2017 DAC8775
An example layout based on the design discussed in the Typical Application section is shown in the Layout Example section. Figure 139 shows the top-layer of the design which illustrates all component placement as no components are placed on the bottom layer. Figure 140 shows two of the internal power-layers: the layer on the left contains VPOS_IN_B, VPOS_IN_C, VNEG_IN_B, and VNEG_IN_D nets while the layer on the right contains VPOS_IN_A, VPOS_IN_D, VNEG_IN_A, and VNEG_IN_C nets.
The layer stack-up for this 6-layer example layout is shown below. A 6-layer design is not required, however provides optimal conditions for ground and power-supply planes. The solid ground plane beneath the majority of the signal traces, which are placed on the top layer, allows for a clean return path for sensitive analog traces and keeps them isolated from the internal power supply nets which will exhibit ripple from the DC/DC converter.
Traces for the DC/DC external components should be as low impedance, low inductance, and low capacitance as possible in order to maintain optimum performance. As such wide traces should be used to minimize inductance with minimal use of vias as vias will contribute large inductance and capacitance to the trace. For this reason it is recommended that all DC/DC components placed on the top layer.
The industrial transient protection circuit should be placed as close to the output connectors as possible to ensure that the return currents from these transients have a controlled path to exit the PCB which does not impact the analog circuitry.
Split ground planes for the DC/DC, digital, and analog grounds are not required but may be helpful to isolated ground return currents from cross-talk. If split ground planes are used care should be taken to ensure that signal traces are only placed above or below the locations where their respective grounds are placed in order to mitigate unexpected return paths or coupling to the other ground planes. If a single ground plane is used it is advisable to follow similar practices implementing a star-ground where the respective return currents interact with one another minimally. The example layout uses a single ground plane, based on measured results, performs similarly to an identical version with split ground planes.
The perimeter of the board is stitched with vias in order to enhance design performance against environments which may include radiated emissions. Additional vias are placed in critical areas nearby the design in order to place ground pours in between nodes to reduce cross-talk between adjacent traces.
Standard best-practices should be applied to the remaining components, including but not limited to, placing decoupling capacitors close to their respective pins and using wide traces or copper pours where possible, particularly for power traces where high current may flow.