DLPS136 November   2018 DLP650LNIR

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Micromirror Array Physical Characteristics
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 System Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DLPC410: Digital Controller for DLP Discovery 4100 Chipset
      2. 7.3.2 DLPA200: DMD Micromirror Driver
      3. 7.3.3 DLPR410: PROM for DLP Discovery 4100 Chipset
      4. 7.3.4 DLP650LNIR: DLP 0.65 WXGA NIR 2xLVDS Series 450 DMD
        1. 7.3.4.1 DLP650LNIR Chipset Interfaces
          1. 7.3.4.1.1 DLPC410 Interface Description
            1. 7.3.4.1.1.1 DLPC410 IO
            2. 7.3.4.1.1.2 Initialization
            3. 7.3.4.1.1.3 DMD Device Detection
            4. 7.3.4.1.1.4 Power Down
          2. 7.3.4.1.2 DLPC410 to DMD Interface
            1. 7.3.4.1.2.1 DLPC410 to DMD IO Description
            2. 7.3.4.1.2.2 Data Flow
          3. 7.3.4.1.3 DLPC410 to DLPA200 Interface
            1. 7.3.4.1.3.1 DLPA200 Operation
            2. 7.3.4.1.3.2 DLPC410 to DLPA200 IO Description
          4. 7.3.4.1.4 DLPA200 to DLP650LNIR Interface
            1. 7.3.4.1.4.1 DLPA200 to DLP650LNIR Interface Overview
      5. 7.3.5 Measurement Conditions
    4. 7.4 Device Operational Modes
      1. 7.4.1 DMD Block Modes
        1. 7.4.1.1 Single Block Mode
        2. 7.4.1.2 Dual Block Mode
        3. 7.4.1.3 Quad Block Mode
        4. 7.4.1.4 Global Mode
      2. 7.4.2 DMD Load4 Mode
    5. 7.5 Feature Description
      1. 7.5.1 Power Interface
      2. 7.5.2 Timing
    6. 7.6 Optical Interface and System Image Quality Considerations
      1. 7.6.1 Optical Interface and System Image Quality
      2. 7.6.2 Numerical Aperture and Stray Light Control
      3. 7.6.3 Pupil Match
      4. 7.6.4 Illumination Overfill
    7. 7.7 Micromirror Temperature Calculations
      1. 7.7.1 Sample Calculation 1: Uniform Illumination of Entire DMD Active Array (1280 × 800 pixels)
      2. 7.7.2 Sample Calculation 2: Partial DMD Active Array Illumination with Non-uniform Illumination Peak
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Description
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Impedance Requirements
      2. 10.1.2 PCB Signal Routing
      3. 10.1.3 Fiducials
      4. 10.1.4 DMD Interface
        1. 10.1.4.1 Trace Length Matching
      5. 10.1.5 DLP650LNIR Decoupling
        1. 10.1.5.1 Decoupling Capacitors
      6. 10.1.6 VCC and VCC2
      7. 10.1.7 DMD Layout
      8. 10.1.8 DLPA200
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

FYL Package
149-Pin CLGA
Bottom View
DLP650LNIR DS-s450-Pins.gif

Pin Functions

PIN NET LENGTH (mils) SIGNAL TYPE(1) DESCRIPTION
NAME NO.
DATA INPUTS
D_AN(1) G20 711.64 LVDS I LVDS pair for Data Bus A
D_AN(3) H19 711.60
D_AN(5) F18 711.60
D_AN(7) E18 711.60
D_AN(9) C20 711.60
D_AN(11) B18 711.60
D_AN(13) A20 711.60
D_AN(15) B19 711.58
D_AP(1) H20 711.66
D_AP(3) G19 711.61
D_AP(5) G18 711.59
D_AP(7) D18 711.60
D_AP(9) D20 711.59
D_AP(11) A18 711.58
D_AP(13) B20 711.59
D_AP(15) A19 711.59
D_BN(1) K20 711.61 LVDS I LVDS pair for Data Bus B
D_BN(3) J19 711.59
D_BN(5) L18 711.59
D_BN(7) M18 711.6
D_BN(9) P20 711.6
D_BN(11) R18 711.59
D_BN(13) T20 711.59
D_BN(15) R19 711.59
D_BP(1) J20 711.61
D_BP(3) K19 711.6
D_BP(5) K18 711.58
D_BP(7) N18 711.58
D_BP(9) N20 711.6
D_BP(11) T18 711.61
D_BP(13) R20 711.59
D_BP(15) T19 711.6
DCLK_AN D19 711.59 I LVDS pair for Data Clock A
DCLK_AP E19 711.59
DCLK_BN N19 711.6 I LVDS pair for Data Clock B
DCLK_BP M19 711.61
DATA CONTROL INPUTS
SCTRL_AN F20 711.62 I LVDS pair for Serial Control (Sync) A
SCTRL_AP E20 711.6
SCTRL_BN L20 711.59 I LVDS pair for Serial Control (Sync) B
SCTRL_BP M20 711.59
MICROMIRROR BIAS RESET INPUTS
MBRST(0) C3 507.20 I Non–logic compatible Micromirror Bias Reset signals. Connected directly to the array of pixel micromirrors. Used to hold or release the micromirrors. Bond Pads connect to an internal pull–down resistor.
MBRST(1) D2 576.83
MBRST(2) D3 545.78
MBRST(3) E2 636.33
MBRST(4) G3 618.42
MBRST(5) E1 738.25
MBRST(6) G2 718.82
MBRST(7) G1 777.04
MBRST(8) N3 543.29
MBRST(9) M2 612.93
MBRST(10) M3 580.97
MBRST(11) L2 672.43
MBRST(12) J3 653.61
MBRST(13) L1 764.00
MBRST(14) J2 764.37
MBRST(15) J1 813.14
SCP CONTROL
SCPCLK A8 I Serial Communications Port Clock. Bond Pad connects to an internal pulldown circuit.
SCPDI A5 I Serial Communications Port Data. Bond Pad connects to an internal pulldown circuit.
SCPENZ B7 I Active low serial communications port enable. Bond pad connects to an internal pulldown circuit.
SCPDO A9 O Serial communications port output.
OTHER SIGNALS
EVCC A3 P Do Not Connect on the DLP system board.
MODE_A A4 415.1 I Data Bus Width Select. Bond Pad connects to an internal pull–down circuit, but for this DMD the PCB also ties this signal to GND.
PWRDNZ B9 110.38 I Active Low Device Reset. Bond Pad connects to an internal pull–down circuit.
POWER
VCC(2) B11, B12, B13, B16, R12, R13, R16, R17 P Power supply for low voltage CMOS logic. Power supply for normal high voltage at micromirror address electrodes.
VCCI(2) A12, A14, A16, T12, T14, T16 P Power supply for low voltage CMOS LVDS interface.
VCC2(2) C1, D1, M1, N1 P Power supply for high voltage CMOS logic. Power supply for stepped high voltage at micromirror address electrodes.
VSS (Ground)(3) A6, A11, A13, A15, A17, B4, B5, B8, B14, B15, B17, C2, C18, C19, F1, F2, F19, H1, H2, H3, H18, J18, K1, K2, L19, N2, P18, P19, R4, R9, R14, R15, T7, T13, T15, T17 P Common Return for all power.
RESERVED SIGNALS
RESERVED_FC R7 40.64 I Connect to GND on the DLP system board. Bond Pad connects to an internal pull–down circuit.
RESERVED_FD R8 94.37 I Connect to GND on the DLP system board. Bond Pad connects to an internal pull–down circuit.
RESERVED_PFE T8 50.74 I Connect to ground on the DLP system board. Bond Pad connects to an internal pull-down circuit.
RESERVED_STM B6 I Connect to GND on the DLP system board. Bond Pad connects to an internal pull–down circuit.
RESERVED_TP0 R10 93.3 I Do not connect on the DLP system board.
RESERVED_TP1 T11 263.74 I Do not connect on the DLP system board.
RESERVED_TP2 R11 281.47 I Do not connect on the DLP system board.
RESERVED_BA T10 148.85 O Do not connect on the DLP system board.
RESERVED_BB A10 105.28 O Do not connect on the DLP system board.
RESERVED_RA1 T9 O Do not connect on the DLP system board.
RESERVED_RB1 A7 O Do not connect on the DLP system board.
RESERVED_TS B10 145.42 O Do not connect on the DLP system board.
RESERVED_A(0) T2 NC Do not connect on the DLP system board.
RESERVED_A(1) T3
RESERVED_A(2) R3
RESERVED_A(3) T4
RESERVED_M(0) R2 NC Do not connect on the DLP system board.
RESERVED_M(1) P1 NC Do not connect on the DLP system board.
RESERVED_S(0) T1 NC Do not connect on the DLP system board.
RESERVED_S(1) R1 NC Do not connect on the DLP system board.
RESERVED_IRQZ T6 NC Do not connect on the DLP system board.
RESERVED_OEZ R5 NC Do not connect on the DLP system board.
RESERVED_RSTZ R6 NC Do not connect on the DLP system board.
RESERVED_STR T5 NC Do not connect on the DLP system board.
RESERVED_STR T5 NC Do not connect on the DLP system board.
RESERVED_VB E3, F3, K3, L3 NC Do not connect on the DLP system board.
RESERVED_VR B2, B3, P2, P3 NC Do not connect on the DLP system board.
(1) I = Input, O = Output, G = Ground, A = Analog, P = Power, NC = No Connect.
(2) Power supply pins required for all DMD operating modes are VSS, VCC, VCCI, VCC2.
(3) VSS must be connected for proper DMD operation.