SNLS505E August   2016  – March 2019 DP83822H , DP83822HF , DP83822I , DP83822IF

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 IO Pins State During Reset
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Power-Up Timing
    7. 7.7  Timing Requirements, Reset Timing
    8. 7.8  Timing Requirements, Serial Management Timing
    9. 7.9  Timing Requirements, 100 Mbps MII Transmit Timing
    10. 7.10 Timing Requirements, 100 Mbps MII Receive Timing
    11. 7.11 Timing Requirements, 10 Mbps MII Transmit Timing
    12. 7.12 Timing Requirements, 10 Mbps MII Receive Timing
    13. 7.13 Timing Requirements, RMII Transmit Timing
    14. 7.14 Timing Requirements, RMII Receive Timing
    15. 7.15 Timing Requirements, RGMII
    16. 7.16 Normal Link Pulse Timing
    17. 7.17 Auto-Negotiation Fast Link Pulse (FLP) Timing
    18. 7.18 10BASE-Te Jabber Timing
    19. 7.19 MII: 100BASE-TX Transmit Latency Timing
    20. 7.20 MII: 100BASE-TX Receive Latency Timing
    21. 7.21 Timing Diagrams
    22. 7.22 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Energy Efficient Ethernet
        1. 8.3.1.1 EEE Overview
        2. 8.3.1.2 EEE Negotiation
      2. 8.3.2 Wake-on-LAN Packet Detection
        1. 8.3.2.1 Magic Packet Structure
        2. 8.3.2.2 Magic Packet Example
        3. 8.3.2.3 Wake-on-LAN Configuration and Status
      3. 8.3.3 Start of Frame Detect for IEEE 1588 Time Stamp
      4. 8.3.4 Clock Output
    4. 8.4 Device Functional Modes
      1. 8.4.1  MAC Interfaces
        1. 8.4.1.1 Media Independent Interface (MII)
        2. 8.4.1.2 Reduced Media Independent Interface (RMII)
        3. 8.4.1.3 Reduced Gigabit Media Independent Interface (RGMII)
      2. 8.4.2  Serial Management Interface
        1. 8.4.2.1 Extended Register Space Access
        2. 8.4.2.2 Write Address Operation
        3. 8.4.2.3 Read Address Operation
        4. 8.4.2.4 Write (No Post Increment) Operation
        5. 8.4.2.5 Read (No Post Increment) Operation
        6. 8.4.2.6 Write (Post Increment) Operation
        7. 8.4.2.7 Read (Post Increment) Operation
        8. 8.4.2.8 Example Write Operation (No Post Increment)
        9. 8.4.2.9 Example Read Operation (No Post Increment)
      3. 8.4.3  100BASE-TX
        1. 8.4.3.1 100BASE-TX Transmitter
          1. 8.4.3.1.1 Code-Group Encoding and Injection
          2. 8.4.3.1.2 Scrambler
          3. 8.4.3.1.3 NRZ to NRZI Encoder
          4. 8.4.3.1.4 Binary to MLT-3 Converter
        2. 8.4.3.2 100BASE-TX Receiver
      4. 8.4.4  100BASE-FX
        1. 8.4.4.1 100BASE-FX Transmit
        2. 8.4.4.2 100BASE-FX Receive
      5. 8.4.5  10BASE-Te
        1. 8.4.5.1 Squelch
        2. 8.4.5.2 Normal Link Pulse Detection and Generation
        3. 8.4.5.3 Jabber
        4. 8.4.5.4 Active Link Polarity Detection and Correction
      6. 8.4.6  Auto-Negotiation (Speed / Duplex Selection)
      7. 8.4.7  Auto-MDIX Resolution
      8. 8.4.8  Loopback Modes
        1. 8.4.8.1 Near-End Loopback
        2. 8.4.8.2 MII Loopback
        3. 8.4.8.3 PCS Loopback
        4. 8.4.8.4 Digital Loopback
        5. 8.4.8.5 Analog Loopback
        6. 8.4.8.6 Far-End (Reverse) Loopback
      9. 8.4.9  BIST Configurations
      10. 8.4.10 Cable Diagnostics
        1. 8.4.10.1 TDR
      11. 8.4.11 Fast Link Down Functionality
    5. 8.5 Programming
      1. 8.5.1 Hardware Bootstrap Configurations
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPI Network Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Fiber Network Circuit
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Clock Requirements
            1. 9.2.2.1.1.1 Oscillator
            2. 9.2.2.1.1.2 Crystal
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 MII Layout Guidelines
          2. 9.2.2.2.2 RMII Layout Guidelines
          3. 9.2.2.2.3 RGMII Layout Guidelines
          4. 9.2.2.2.4 MDI Layout Guidelines
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Characteristics
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Transformer Layout
        1. 11.1.3.1 Transformer Recommendations
      4. 11.1.4 Metal Pour
      5. 11.1.5 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Revision History

Changes from D Revision (March 2019) to E Revision

  • Changed to fix typos on Table 1 Go

Changes from C Revision (April 2018) to D Revision

  • Changed the description for LED_1 in Pin Functions table.Go
  • Changed reset pin state for RX_D[3:0] pins in Table 1Go
  • Added XO and XI capacitanceGo
  • Added Test Conditions to PMD OUTPUT section of the Electrical Characteristics TableGo
  • Changed Parameter descriptions and units in Reset Timing Requirements table to match device performance.Go
  • Changed NOTE for 100BASE-FX Signal Detect pin polarity from Active LOW to Active HIGH.Go
  • Changed LED_0 strap modes to remove Mode 2 and Mode 3. Go
  • Changed strap description for SD_EN pin from Active LOW to Active HIGH.Go
  • Deleted LED_0 configuration table.Go
  • Changed LED_1 Configuration table to merge LED_0 and LED_1 configuration into a single table for clarity.Go
  • Changed note in LED Configuration section to clarify LED connections.Go
  • Added registers 0x0106, 0x0107, 0x01F, 0x0114, 0x0116, 0x0126, 0x04D4, 0x04D5, and 0x04D6 Go
  • Changed FUNCTION column of bits 3 and 2 in Table 37 to swap '0' and '1' functionality. Go
  • Changed SD_EN=0 to SD_EN=1 in Register 0x465 bit 0 FunctionGo
  • Added 100Base-TX MII power consumption data for -40oC and 125oCGo

Changes from B Revision (March 2018) to C Revision

  • Changed TX_D[1:0] back to TX_D[3:0]Go
  • Changed RX_D[1:0] back to RX_D[3:0]Go

Changes from A Revision (August 2016) to B Revision

  • Updated data sheet text and format to the latest TI documentation and translations standards Go
  • Updated description of pin 24 and changed pin type from: I/O, PD to: I/O Go
  • Added MII: 100BASE-TX Transmit Latency Timing table Go
  • Added MII: 100BASE-TX Receive Latency Timing table Go
  • Device Power-Up Timing diagram modified to include start voltage limitsGo
  • Added the 100BASE-TX Transmit Latency Timing graphic Go
  • Added the 100BASE-TX Receive Latency Timing graphic Go
  • Changed the Functional Block DiagramGo
  • Changed TX_D[3:0] to TX_D[1:0]Go
  • Changed RX_D[3:0] to RX_D[1:0]Go
  • Added note to the 100BASE-FX Receive section and changed the SD_DIS pin to SD_ENGo
  • Changed RX_ER strap function from: AMDIX_EN (SD_DIS) to: AMDIX_EN (SD_EN)Go
  • Changed the default and switched 0 and 1 functions for the RMII Recovered Clock Async FIFO Bypass bit in RCSR register (0X0017)Go
  • Changed the 0x7D BIST IPG length from: 125 bytes to: 500 bytes Go
  • Added 0 and 1 functions for the MLED Polarity Swap bit in the MLEDCR register (0x0025)Go
  • Added Line Driver Class Selection (LDCSEL) registerGo
  • Changed 0x0465 register from: General Configuration to: Fiber General Configuration and switched the Active HIGH and LOW polarities for 1 and 0Go
  • Changed the 100Base-FX Signal Detect Polarity bit description noteGo
  • Changed Pattern Start Point bit default from: 0 to: 01100Go
  • Added the Detailed Design Procedure section for the TPI Network Circuit typical applicationGo
  • Added note to the Oscillator section Go
  • Changed the Power Connections graphic Go

Changes from * Revision (August 2016) to A Revision

  • Changed Product Preview to Production Data release Go