SNLS647B December   2019  – March 2020 DP83826E , DP83826I

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application
  4. Revision History
  5. Mode Comparison Tables
  6. Pin Configuration and Functions (ENHANCED Mode)
    1.     Pin Functions (ENHANCED Mode)
  7. Pin Configuration and Functions (BASIC Mode)
    1.     Pin Functions (BASIC Mode)
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Auto-Negotiation (Speed/Duplex Selection)
      2. 9.3.2  Auto-MDIX Resolution
      3. 9.3.3  Wake-on-LAN Packet Detection
        1. 9.3.3.1 Magic Packet Structure
        2. 9.3.3.2 Magic Packet Example
        3. 9.3.3.3 Wake-on-LAN Configuration and Status
      4. 9.3.4  Low Power Modes
        1. 9.3.4.1 Active Sleep
        2. 9.3.4.2 IEEE Power-Down
        3. 9.3.4.3 Deep Power Down State
      5. 9.3.5  RMII Repeater Mode
      6. 9.3.6  Clock Output
      7. 9.3.7  Media Independent Interface (MII)
      8. 9.3.8  Reduced Media Independent Interface (RMII)
      9. 9.3.9  Serial Management Interface
        1. 9.3.9.1 Extended Register Space Access
        2. 9.3.9.2 Write Address Operation
        3. 9.3.9.3 Read Address Operation
        4. 9.3.9.4 Write (No Post Increment) Operation
        5. 9.3.9.5 Read (No Post Increment) Operation
        6. 9.3.9.6 Example Write Operation (No Post Increment)
      10. 9.3.10 100BASE-TX
        1. 9.3.10.1 100BASE-TX Transmitter
          1. 9.3.10.1.1 Code-Group Encoding and Injection
          2. 9.3.10.1.2 Scrambler
          3. 9.3.10.1.3 NRZ to NRZI Encoder
          4. 9.3.10.1.4 Binary to MLT-3 Converter
        2. 9.3.10.2 100BASE-TX Receiver
      11. 9.3.11 10BASE-Te
        1. 9.3.11.1 Squelch
        2. 9.3.11.2 Normal Link Pulse Detection and Generation
        3. 9.3.11.3 Jabber
        4. 9.3.11.4 Active Link Polarity Detection and Correction
      12. 9.3.12 Loopback Modes
        1. 9.3.12.1 Near-end Loopback
        2. 9.3.12.2 MII Loopback
        3. 9.3.12.3 PCS Loopback
        4. 9.3.12.4 Digital Loopback
        5. 9.3.12.5 Analog Loopback
        6. 9.3.12.6 Far-End (Reverse) Loopback
      13. 9.3.13 BIST Configurations
      14. 9.3.14 Cable Diagnostics
        1. 9.3.14.1 Time Domain Reflectometry (TDR)
        2. 9.3.14.2 Fast Link-Drop Functionality
      15. 9.3.15 LED and GPIO Configuration
    4. 9.4 Programming
      1. 9.4.1 Hardware Bootstraps Configuration
        1. 9.4.1.1 DP83826 Bootstrap Configurations (ENHANCED Mode)
          1. 9.4.1.1.1 Bootstraps for PHY Address
        2. 9.4.1.2 DP83826 Strap Configuration (BASIC Mode)
          1. 9.4.1.2.1 Bootstraps for PHY Address
    5. 9.5 Register Maps
      1. 9.5.1  BMCR Register (Address = 0x0) [reset = 0x3100]
        1. Table 23. BMCR Register Field Descriptions
      2. 9.5.2  BMSR Register (Address = 0x1) [reset = 0x7849]
        1. Table 24. BMSR Register Field Descriptions
      3. 9.5.3  PHYIDR1 Register (Address = 0x2) [reset = 0x2000]
        1. Table 25. PHYIDR1 Register Field Descriptions
      4. 9.5.4  PHYIDR2 Register (Address = 0x3) [reset = 0xA130]
        1. Table 26. PHYIDR2 Register Field Descriptions
      5. 9.5.5  ANAR Register (Address = 0x4) [reset = 0x1E1]
        1. Table 27. ANAR Register Field Descriptions
      6. 9.5.6  ALNPAR Register (Address = 0x5) [reset = 0x0]
        1. Table 28. ALNPAR Register Field Descriptions
      7. 9.5.7  ANER Register (Address = 0x6) [reset = 0x4]
        1. Table 29. ANER Register Field Descriptions
      8. 9.5.8  ANNPTR Register (Address = 0x7) [reset = 0x2001]
        1. Table 30. ANNPTR Register Field Descriptions
      9. 9.5.9  ANLNPTR Register (Address = 0x8) [reset = 0x0]
        1. Table 31. ANLNPTR Register Field Descriptions
      10. 9.5.10 CR1 Register (Address = 0x9) [reset = 0x0]
        1. Table 32. CR1 Register Field Descriptions
      11. 9.5.11 CR2 Register (Address = 0xA) [reset = 0x0]
        1. Table 33. CR2 Register Field Descriptions
      12. 9.5.12 CR3 Register (Address = 0xB) [reset = 0x0]
        1. Table 34. CR3 Register Field Descriptions
      13. 9.5.13 REGCR Register (Address = 0xD) [reset = 0x0]
        1. Table 35. REGCR Register Field Descriptions
      14. 9.5.14 ADDAR Register (Address = 0xE) [reset = 0x0]
        1. Table 36. ADDAR Register Field Descriptions
      15. 9.5.15 FLDS Register (Address = 0xF) [reset = 0x0]
        1. Table 37. FLDS Register Field Descriptions
      16. 9.5.16 PHYSTS Register (Address = 0x10) [reset = 0x6]
        1. Table 38. PHYSTS Register Field Descriptions
      17. 9.5.17 PHYSCR Register (Address = 0x11) [reset = 0x108]
        1. Table 39. PHYSCR Register Field Descriptions
      18. 9.5.18 MISR1 Register (Address = 0x12) [reset = 0x0]
        1. Table 40. MISR1 Register Field Descriptions
      19. 9.5.19 MISR2 Register (Address = 0x13) [reset = 0x0]
        1. Table 41. MISR2 Register Field Descriptions
      20. 9.5.20 FCSCR Register (Address = 0x14) [reset = 0x0]
        1. Table 42. FCSCR Register Field Descriptions
      21. 9.5.21 RECR Register (Address = 0x15) [reset = 0x0]
        1. Table 43. RECR Register Field Descriptions
      22. 9.5.22 BISCR Register (Address = 0x16) [reset = 0x100]
        1. Table 44. BISCR Register Field Descriptions
      23. 9.5.23 RCSR Register (Address = 0x17) [reset = 0x1]
        1. Table 45. RCSR Register Field Descriptions
      24. 9.5.24 LEDCR Register (Address = 0x18) [reset = 0x480]
        1. Table 46. LEDCR Register Field Descriptions
      25. 9.5.25 PHYCR Register (Address = 0x19) [reset = 0x8000]
        1. Table 47. PHYCR Register Field Descriptions
      26. 9.5.26 10BTSCR Register (Address = 0x1A) [reset = 0x0]
        1. Table 48. 10BTSCR Register Field Descriptions
      27. 9.5.27 BICSR1 Register (Address = 0x1B) [reset = 0x7D]
        1. Table 49. BICSR1 Register Field Descriptions
      28. 9.5.28 BICSR2 Register (Address = 0x1C) [reset = 0x5EE]
        1. Table 50. BICSR2 Register Field Descriptions
      29. 9.5.29 CDCR Register (Address = 0x1E) [reset = 0x0]
        1. Table 51. CDCR Register Field Descriptions
      30. 9.5.30 PHYRCR Register (Address = 0x1F) [reset = 0x0]
        1. Table 52. PHYRCR Register Field Descriptions
      31. 9.5.31 MLEDCR Register (Address = 0x25) [reset = 0x41]
        1. Table 53. MLEDCR Register Field Descriptions
      32. 9.5.32 COMPT Register (Address = 0x27) [reset = 0x0]
        1. Table 54. COMPT Register Field Descriptions
      33. 9.5.33 10M_CFG Register (Address = 0x2A) [reset = 0x4000]
        1. Table 55. 10M_CFG Register Field Descriptions
      34. 9.5.34 FLD_CFG1 Register (Address = 0x117) [reset = 0x0]
        1. Table 56. FLD_CFG1 Register Field Descriptions
      35. 9.5.35 FLD_CFG2 Register (Address = 0x131) [reset = 0x0]
        1. Table 57. FLD_CFG2 Register Field Descriptions
      36. 9.5.36 CDSCR Register (Address = 0x170) [reset = 0x410]
        1. Table 58. CDSCR Register Field Descriptions
      37. 9.5.37 CDSCR2 Register (Address = 0x171) [reset = 0x0]
        1. Table 59. CDSCR2 Register Field Descriptions
      38. 9.5.38 TDR_172 Register (Address = 0x172) [reset = 0x0]
        1. Table 60. TDR_172 Register Field Descriptions
      39. 9.5.39 CDSCR3 Register (Address = 0x173) [reset = 0xD04]
        1. Table 61. CDSCR3 Register Field Descriptions
      40. 9.5.40 TDR_174 Register (Address = 0x174) [reset = 0x0]
        1. Table 62. TDR_174 Register Field Descriptions
      41. 9.5.41 TDR_175 Register (Address = 0x175) [reset = 0x1004]
        1. Table 63. TDR_175 Register Field Descriptions
      42. 9.5.42 TDR_176 Register (Address = 0x176) [reset = 0x5]
        1. Table 64. TDR_176 Register Field Descriptions
      43. 9.5.43 CDSCR4 Register (Address = 0x177) [reset = 0x1E00]
        1. Table 65. CDSCR4 Register Field Descriptions
      44. 9.5.44 TDR_178 Register (Address = 0x178) [reset = 0x2]
        1. Table 66. TDR_178 Register Field Descriptions
      45. 9.5.45 CDLRR1 Register (Address = 0x180) [reset = 0x0]
        1. Table 67. CDLRR1 Register Field Descriptions
      46. 9.5.46 CDLRR2 Register (Address = 0x181) [reset = 0x0]
        1. Table 68. CDLRR2 Register Field Descriptions
      47. 9.5.47 CDLRR3 Register (Address = 0x182) [reset = 0x0]
        1. Table 69. CDLRR3 Register Field Descriptions
      48. 9.5.48 CDLRR4 Register (Address = 0x183) [reset = 0x0]
        1. Table 70. CDLRR4 Register Field Descriptions
      49. 9.5.49 CDLRR5 Register (Address = 0x184) [reset = 0x0]
        1. Table 71. CDLRR5 Register Field Descriptions
      50. 9.5.50 CDLAR1 Register (Address = 0x185) [reset = 0x0]
        1. Table 72. CDLAR1 Register Field Descriptions
      51. 9.5.51 CDLAR2 Register (Address = 0x186) [reset = 0x0]
        1. Table 73. CDLAR2 Register Field Descriptions
      52. 9.5.52 CDLAR3 Register (Address = 0x187) [reset = 0x0]
        1. Table 74. CDLAR3 Register Field Descriptions
      53. 9.5.53 CDLAR4 Register (Address = 0x188) [reset = 0x0]
        1. Table 75. CDLAR4 Register Field Descriptions
      54. 9.5.54 CDLAR5 Register (Address = 0x189) [reset = 0x0]
        1. Table 76. CDLAR5 Register Field Descriptions
      55. 9.5.55 CDLAR6 Register (Address = 0x18A) [reset = 0x0]
        1. Table 77. CDLAR6 Register Field Descriptions
      56. 9.5.56 IO_CFG1 Register (Address = 0x302) [reset = 0x0]
        1. Table 78. IO_CFG1 Register Field Descriptions
      57. 9.5.57 LED0_GPIO_CFG Register (Address = 0x303) [reset = 0x8]
        1. Table 79. LED0_GPIO_CFG Register Field Descriptions
      58. 9.5.58 LED1_GPIO_CFG Register (Address = 0x304) [reset = 0xD]
        1. Table 80. LED1_GPIO_CFG Register Field Descriptions
      59. 9.5.59 LED2_GPIO_CFG Register (Address = 0x305) [reset = 0x0]
        1. Table 81. LED2_GPIO_CFG Register Field Descriptions
      60. 9.5.60 LED3_GPIO_CFG Register (Address = 0x306) [reset = 0x0]
        1. Table 82. LED3_GPIO_CFG Register Field Descriptions
      61. 9.5.61 CLK_OUT_LED_STATUS Register (Address = 0x308) [reset = 0x0]
        1. Table 83. CLK_OUT_LED_STATUS Register Field Descriptions
      62. 9.5.62 VOD_CFG1 Register (Address = 0x30B) [reset = 0xC00]
        1. Table 84. VOD_CFG1 Register Field Descriptions
      63. 9.5.63 VOD_CFG2 Register (Address = 0x30C) [reset = 0x410]
        1. Table 85. VOD_CFG2 Register Field Descriptions
      64. 9.5.64 VOD_CFG3 Register (Address = 0x30E) [reset = 0x0]
        1. Table 86. VOD_CFG3 Register Field Descriptions
      65. 9.5.65 ANA_LD_PROG_SL Register (Address = 0x404) [reset = 0x0]
        1. Table 87. ANA_LD_PROG_SL Register Field Descriptions
      66. 9.5.66 ANA_RX10BT_CTRL Register (Address = 0x40D) [reset = 0x0]
        1. Table 88. ANA_RX10BT_CTRL Register Field Descriptions
      67. 9.5.67 GENCFG Register (Address = 0x456) [reset = 0x8]
        1. Table 89. GENCFG Register Field Descriptions
      68. 9.5.68 PIN_CFG1 Register (Address = 0x459) [reset = 0x0]
        1. Table 90. PIN_CFG1 Register Field Descriptions
      69. 9.5.69 PIN_CFG2 Register (Address = 0x45A) [reset = 0x0]
        1. Table 91. PIN_CFG2 Register Field Descriptions
      70. 9.5.70 LEDCFG Register (Address = 0x460) [reset = 0x650]
        1. Table 92. LEDCFG Register Field Descriptions
      71. 9.5.71 IOCTRL Register (Address = 0x461) [reset = 0x0]
        1. Table 93. IOCTRL Register Field Descriptions
      72. 9.5.72 SOR1 Register (Address = 0x467) [reset = 0x0]
        1. Table 94. SOR1 Register Field Descriptions
      73. 9.5.73 SOR2 Register (Address = 0x468) [reset = 0x87]
        1. Table 95. SOR2 Register Field Descriptions
      74. 9.5.74 LEDCFG2 Register (Address = 0x469) [reset = 0x40]
        1. Table 96. LEDCFG2 Register Field Descriptions
      75. 9.5.75 RXFCFG1 Register (Address = 0x4A0) [reset = 0x1081]
        1. Table 97. RXFCFG1 Register Field Descriptions
      76. 9.5.76 RXFS Register (Address = 0x4A1) [reset = 0x1000]
        1. Table 98. RXFS Register Field Descriptions
      77. 9.5.77 RXFPMD1 Register (Address = 0x4A2) [reset = 0x0]
        1. Table 99. RXFPMD1 Register Field Descriptions
      78. 9.5.78 RXFPMD2 Register (Address = 0x4A3) [reset = 0x0]
        1. Table 100. RXFPMD2 Register Field Descriptions
      79. 9.5.79 RXFPMD3 Register (Address = 0x4A4) [reset = 0x0]
        1. Table 101. RXFPMD3 Register Field Descriptions
      80. 9.5.80 RXFSOP1 Register (Address = 0x4A5) [reset = 0x0]
        1. Table 102. RXFSOP1 Register Field Descriptions
      81. 9.5.81 RXFSOP2 Register (Address = 0x4A6) [reset = 0x0]
        1. Table 103. RXFSOP2 Register Field Descriptions
      82. 9.5.82 RXFSOP3 Register (Address = 0x4A7) [reset = 0x0]
        1. Table 104. RXFSOP3 Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Twisted-Pair Interface (TPI) Network Circuit
      2. 10.2.2 Design Requirements
        1. 10.2.2.1 Clock Requirements
          1. 10.2.2.1.1 Oscillator
          2. 10.2.2.1.2 Crystal
      3. 10.2.3 Detailed Design Procedure
        1. 10.2.3.1 MII Layout Guidelines
        2. 10.2.3.2 RMII Layout Guidelines
        3. 10.2.3.3 MDI Layout Guidelines
      4. 10.2.4 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Signal Traces
      2. 12.1.2 Return Path
      3. 12.1.3 Transformer Layout
        1. 12.1.3.1 Transformer Recommendations
      4. 12.1.4 Metal Pour
      5. 12.1.5 PCB Layer Stacking
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Low and deterministic latency
    • TX latency: 40 ns, RX latency: 170 ns
    • Deterministic latency over power cycles < ±2 ns
    • Fixed phase XI to TX_CLK relationship < ±2 ns
  • Robust and small system solution
  • Two selectable pin modes in single device
    • ENHANCED mode for additional features
    • BASIC mode for common Ethernet pinout
  • Low power consumption < 160 mW
  • MAC interfaces: MII, RMII
  • Programmable energy-saving modes
    • Active sleep
    • Deep power down
    • Wake-on-LAN (WoL)
  • Diagnostic tools: cable diagnostics, built-in self-test (BIST), loopback modes
  • Single, 3.3-V power supply
  • I/O voltages: 1.8 V or 3.3 V
  • RMII back-to-back repeater mode
  • DP83826E operating temperature range: –40°C to 105°C
  • DP83826I operating temperature range: –40°C to 85°C
  • IEEE 802.3 compliant: 10BASE-Te, 100BASE-TX