SPRS960G June   2016  – November 2019 DRA710 , DRA712 , DRA714 , DRA716 , DRA718

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 ATL
      25. 4.3.25 Emulation and Debug Subsystem
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Sysboot
        2. 4.3.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.26.3 System Direct Memory Access (SDMA)
        4. 4.3.26.4 Interrupt Controllers (INTC)
      27. 4.3.27 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-13 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-14 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
          3. 5.10.4.3.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-56 Timing Requirements for I2C Input Timings
          2. Table 5-57 Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
          3. Table 5-58 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 HDQ1W
          1. 5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
        12. 5.10.6.12 UART
          1. Table 5-63 Timing Requirements for UART
          2. Table 5-64 Switching Characteristics Over Recommended Operating Conditions for UART
        13. 5.10.6.13 McSPI
        14. 5.10.6.14 QSPI
        15. 5.10.6.15 McASP
          1. Table 5-71 Timing Requirements for McASP1
          2. Table 5-72 Timing Requirements for McASP2
          3. Table 5-73 Timing Requirements for McASP3/4/5/6/7/8
        16. 5.10.6.16 USB
          1. 5.10.6.16.1 USB1 DRD PHY
          2. 5.10.6.16.2 USB2 PHY
          3. 5.10.6.16.3 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 DCAN
          1. Table 5-91 Timing Requirements for DCANx Receive
          2. Table 5-92 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-93 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-94 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-95 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-96 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-101 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-102 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-104 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-108 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-109 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-111 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.21.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.21.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.21.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-142 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 PRU-ICSS
          1. 5.10.6.23.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.23.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-164 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-165 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.23.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.23.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-167 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-168 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.23.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-169 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-170 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-171 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.23.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.23.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-173 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-175 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-176 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.23.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.23.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-177 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-178 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-179 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.23.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-180 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-181 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-182 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-183 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.23.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-184 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-185 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.23.5 PRU-ICSS IOSETs
          6. 5.10.6.23.6 PRU-ICSS Manual Functional Mapping
        24. 5.10.6.24 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-202 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-203 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-204 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-205 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IVA
    6. 6.6  IPU
    7. 6.7  GPU
    8. 6.8  BB2D
    9. 6.9  PRU-ICSS
    10. 6.10 Memory Subsystem
      1. 6.10.1 EMIF
      2. 6.10.2 GPMC
      3. 6.10.3 ELM
      4. 6.10.4 OCMC
    11. 6.11 Interprocessor Communication
      1. 6.11.1 MailBox
      2. 6.11.2 Spinlock
    12. 6.12 Interrupt Controller
    13. 6.13 EDMA
    14. 6.14 Peripherals
      1. 6.14.1  VIP
      2. 6.14.2  DSS
      3. 6.14.3  Timers
        1. 6.14.3.1 General-Purpose Timers
        2. 6.14.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.14.3.3 Watchdog Timer
      4. 6.14.4  I2C
      5. 6.14.5  UART
        1. 6.14.5.1 UART Features
        2. 6.14.5.2 IrDA Features
        3. 6.14.5.3 CIR Features
      6. 6.14.6  McSPI
      7. 6.14.7  QSPI
      8. 6.14.8  McASP
      9. 6.14.9  USB
      10. 6.14.10 PCIe
      11. 6.14.11 DCAN
      12. 6.14.12 GMAC_SW
      13. 6.14.13 eMMC/SD/SDIO
      14. 6.14.14 GPIO
      15. 6.14.15 ePWM
      16. 6.14.16 eCAP
      17. 6.14.17 eQEP
    15. 6.15 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 Power Regulators
        3. 7.5.2.3 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 PCIe Board Design and Layout Guidelines
        1. 7.5.5.1 PCIe Connections and Interface Compliance
          1. 7.5.5.1.1 Coupling Capacitors
          2. 7.5.5.1.2 Polarity Inversion
        2. 7.5.5.2 Non-standard PCIe connections
          1. 7.5.5.2.1 PCB Stackup Specifications
          2. 7.5.5.2.2 Routing Specifications
            1. 7.5.5.2.2.1 Impedance
            2. 7.5.5.2.2.2 Differential Coupling
            3. 7.5.5.2.2.3 Pair Length Matching
        3. 7.5.5.3 LJCB_REFN/P Connections
      6. 7.5.6 CSI2 Board Design and Routing Guidelines
        1. 7.5.6.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.6.1.1 General Guidelines
          2. 7.5.6.1.2 Length Mismatch Guidelines
            1. 7.5.6.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.6.1.3 Frequency-domain Specification Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR3 Board Design and Layout Guidelines
        1. 7.7.2.1  Board Designs
        2. 7.7.2.2  DDR3 EMIF
        3. 7.7.2.3  DDR3 Device Combinations
        4. 7.7.2.4  DDR3 Interface Schematic
          1. 7.7.2.4.1 32-Bit DDR3 Interface
          2. 7.7.2.4.2 16-Bit DDR3 Interface
        5. 7.7.2.5  Compatible JEDEC DDR3 Devices
        6. 7.7.2.6  PCB Stackup
        7. 7.7.2.7  Placement
        8. 7.7.2.8  DDR3 Keepout Region
        9. 7.7.2.9  Bulk Bypass Capacitors
        10. 7.7.2.10 High-Speed Bypass Capacitors
          1. 7.7.2.10.1 Return Current Bypass Capacitors
        11. 7.7.2.11 Net Classes
        12. 7.7.2.12 DDR3 Signal Termination
        13. 7.7.2.13 VREF_DDR Routing
        14. 7.7.2.14 VTT
        15. 7.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.2.15.1 Four DDR3 Devices
            1. 7.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.2.15.2 Two DDR3 Devices
            1. 7.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.2.15.3 One DDR3 Device
            1. 7.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.2.16 Data Topologies and Routing Definition
          1. 7.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.2.17 Routing Specification
          1. 7.7.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.2.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CBD|538
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.10.6.4 DSS

Two Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 2 and DPI Video Output 3.

NOTE

The DPI Video Output i (i = 2, 3) interface is also referred to as VOUTi.

Every VOUT interface consists of:

  • 24-bit data bus (data[23:0])
  • Horizontal synchronization signal (HSYNC)
  • Vertical synchronization signal (VSYNC)
  • Data enable (DE)
  • Field ID (FID)
  • Pixel clock (CLK)

NOTE

For more information, see the Display Subsystem chapter of the Device TRM.

CAUTION

The I/O Timings provided in this section are valid only if signals within a single IOSET are used. The IOSETs are defined in Table 5-43.

CAUTION

The I/O Timings provided in this section are valid only for some DSS usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

CAUTION

All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).

Table 5-39, Table 5-40 through Table 5-42 assume testing over the recommended operating conditions and electrical characteristic conditions.

Table 5-39 DPI Video Output i (i = 2, 3) Default Switching Characteristics(1)(2)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk DPI2/3 11.76 ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P × 0.5-1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P × 0.5-1 (1) ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI2 (vin2a_fld0 clock reference) -2.5 2.5 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI2 (vin2a_fld0 clock reference) -2.5 2.5 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI3 -2.5 2.5 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI3 -2.5 2.5 ns
  1. P = output vouti_clk period in ns.
  2. All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
  3. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note Optimizing DRA7xx and TDA2xx Processors for Use With Video Display SerDes for additional guidance.

Table 5-40 DPI Video Output i (i = 2, 3) Alternate Switching Characteristics(2)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk DPI2/3 6.06 ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P × 0.5-1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P × 0.5-1 (1) ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI2 (vin2a_fld0 clock reference) 1.51 4.55 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI2 (vin2a_fld0 clock reference) 1.51 4.55 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI3 1.51 4.55 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI3 1.51 4.55 ns
  1. P = output vouti_clk period in ns.
  2. All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
  3. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note Optimizing DRA7xx and TDA2xx Processors for Use With Video Display SerDes for additional guidance.

Table 5-41 DPI Video Output i (i = 2, 3) MANUAL4 Switching Characteristics (2)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk DPI2/3 6.06 (3) ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P*0.5-1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P*0.5-1 (1) ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI1 2.85 5.56 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI1 2.85 5.56 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI2 (vin2a_fld0 clock reference) 2.85 5.56 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI2 (vin2a_fld0 clock reference) 2.85 5.56 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI2 (xref_clk2 clock reference) 2.85 5.56 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI2 (xref_clk2 clock reference) 2.85 5.56 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI3 2.85 5.56 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI3 2.85 5.56 ns
  1. P = output vouti_clk period in ns.
  2. All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
  3. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note Optimizing DRA7xx and TDA2xx Processors for Use With Video Display SerDes for additional guidance.

Table 5-42 DPI Video Output i (i = 2, 3) MANUAL5 Switching Characteristics (2)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk DPI2/3 6.06 (3) ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P*0.5-1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P*0.5-1 (1) ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI1 3.55 6.61 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI1 3.55 6.61 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI2 (vin2a_fld0 clock reference) 3.55 6.61 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI2 (vin2a_fld0 clock reference) 3.55 6.61 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI2 (xref_clk2 clock reference) 3.55 6.61 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI2 (xref_clk2 clock reference) 3.55 6.61 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI3 3.55 6.61 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI3 3.55 6.61 ns
  1. P = output vouti_clk period in ns.
  2. All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
  3. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note Optimizing DRA7xx and TDA2xx Processors for Use With Video Display SerDes for additional guidance.
DRA710 DRA712 DRA714 DRA716 DRA718 SPRS906_TIMING_DSS_01.gifFigure 5-22 DPI Video Output(1)(2)(3)
  1. The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
  2. The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
  3. The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.

In Table 5-43 are presented the specific groupings of signals (IOSET) for use with VOUT2.

Table 5-43 VOUT2 IOSETs

SIGNALS IOSET1
BALL MUX
vout2_d23 C8 4
vout2_d22 B9 4
vout2_d21 A7 4
vout2_d20 A9 4
vout2_d19 A8 4
vout2_d18 A11 4
vout2_d17 F10 4
vout2_d16 A10 4
vout2_d15 B10 4
vout2_d14 E10 4
vout2_d13 D10 4
vout2_d12 C10 4
vout2_d11 B11 4
vout2_d10 D11 4
vout2_d9 C11 4
vout2_d8 B12 4
vout2_d7 A12 4
vout2_d6 A13 4
vout2_d5 E11 4
vout2_d4 F11 4
vout2_d3 B13 4
vout2_d2 E13 4
vout2_d1 C13 4
vout2_d0 D13 4
vout2_vsync B8 4
vout2_hsync E8 4
vout2_clk C7 4
vout2_fld D8 4
vout2_de B7 4

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presented in Table 4-32 and described in Device TRM, Control Module Chapter.

Virtual IO Timings Modes must be used to ensure some IO timings for VOUT3. See Table 5-29Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 5-44Virtual Functions Mapping for VOUT3 for a definition of the Virtual modes.

Table 5-44 presents the values for DELAYMODE bitfield.

Table 5-44 Virtual Functions Mapping for DSS VOUT3

BALL BALL NAME Delay Mode Value MUXMODE
DSS_VIRTUAL1 3
B4 gpmc_ad15 14 vout3_d15
K4 gpmc_a8 15 vout3_hsync
D1 gpmc_ad4 14 vout3_d4
F1 gpmc_ad0 14 vout3_d0
C4 gpmc_ad13 14 vout3_d13
L2 gpmc_a2 15 vout3_d18
E2 gpmc_ad1 14 vout3_d1
K3 gpmc_a4 15 vout3_d20
J1 gpmc_a6 15 vout3_d22
A3 gpmc_ad14 14 vout3_d14
M2 gpmc_a1 15 vout3_d17
G3 gpmc_cs3 15 vout3_clk
H1 gpmc_a9 15 vout3_vsync
B3 gpmc_ad11 14 vout3_d11
B1 gpmc_ad6 14 vout3_d6
E1 gpmc_ad2 14 vout3_d2
C1 gpmc_ad3 14 vout3_d3
K1 gpmc_a7 15 vout3_d23
L1 gpmc_a3 15 vout3_d19
A2 gpmc_ad10 14 vout3_d10
B2 gpmc_ad7 14 vout3_d7
J2 gpmc_a10 15 vout3_de
K2 gpmc_a5 15 vout3_d21
C2 gpmc_ad8 14 vout3_d8
D2 gpmc_ad5 14 vout3_d5
M1 gpmc_a0 15 vout3_d16
C3 gpmc_ad12 14 vout3_d12
L3 gpmc_a11 15 vout3_fld
D3 gpmc_ad9 14 vout3_d9

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to ensure some IO timings for VOUT2. See Table 5-29, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-45, Manual Functions Mapping for DSS VOUT2 IOSET1 for a definition of the Manual modes.

Table 5-45 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-45 Manual Functions Mapping for DSS VOUT2 IOSET1

BALL BALL NAME VOUT2_IOSET1
_MANUAL1		 VOUT2_IOSET1
_MANUAL2		 VOUT2_IOSET1
_MANUAL3		 VOUT2_IOSET1
_MANUAL4		 VOUT2_IOSET1
_MANUAL5		 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 4
D8 vin2a_clk0 2571 0 1059 0 1025 0 4110 0 4980 0 CFG_VIN2A_CLK0_OUT vout2_fld
C8 vin2a_d0 2124 0 589 0 577 0 3613 0 4483 0 CFG_VIN2A_D0_OUT vout2_d23
B9 vin2a_d1 2103 0 568 0 557 0 3442 0 4312 0 CFG_VIN2A_D1_OUT vout2_d22
D10 vin2a_d10 2091 0 557 0 545 0 3430 0 4200 0 CFG_VIN2A_D10_OUT vout2_d13
C10 vin2a_d11 2142 0 608 0 596 0 3481 0 4251 0 CFG_VIN2A_D11_OUT vout2_d12
B11 vin2a_d12 2920 385 1816 255 1783 276 3943 601 4713 601 CFG_VIN2A_D12_OUT vout2_d11
D11 vin2a_d13 2776 322 1872 192 1838 213 3799 538 4669 538 CFG_VIN2A_D13_OUT vout2_d10
C11 vin2a_d14 2904 0 1769 0 1757 0 3869 174 4739 174 CFG_VIN2A_D14_OUT vout2_d9
B12 vin2a_d15 2670 257 1665 127 1632 148 3792 473 4662 473 CFG_VIN2A_D15_OUT vout2_d8
A12 vin2a_d16 2814 155 1908 31 1878 43 3837 371 4707 371 CFG_VIN2A_D16_OUT vout2_d7
A13 vin2a_d17 3002 199 1897 69 1865 89 4024 415 4894 415 CFG_VIN2A_D17_OUT vout2_d6
E11 vin2a_d18 1893 0 358 0 347 0 3432 0 4302 0 CFG_VIN2A_D18_OUT vout2_d5
F11 vin2a_d19 1698 0 163 0 151 0 3237 0 4007 0 CFG_VIN2A_D19_OUT vout2_d4
A7 vin2a_d2 2193 0 658 0 646 0 3531 0 4401 0 CFG_VIN2A_D2_OUT vout2_d21
B13 vin2a_d20 1736 0 202 0 190 0 3075 0 3945 0 CFG_VIN2A_D20_OUT vout2_d3
E13 vin2a_d21 1636 0 101 0 89 0 3074 0 3944 0 CFG_VIN2A_D21_OUT vout2_d2
C13 vin2a_d22 1628 0 93 0 81 0 3266 0 4036 0 CFG_VIN2A_D22_OUT vout2_d1
D13 vin2a_d23 1538 0 0 0 0 0 2968 0 3838 0 CFG_VIN2A_D23_OUT vout2_d0
A9 vin2a_d3 1997 0 462 0 450 0 3335 0 4205 0 CFG_VIN2A_D3_OUT vout2_d20
A8 vin2a_d4 2528 0 993 0 982 0 3867 0 4537 0 CFG_VIN2A_D4_OUT vout2_d19
A11 vin2a_d5 2038 0 503 0 492 0 3577 0 4347 0 CFG_VIN2A_D5_OUT vout2_d18
F10 vin2a_d6 1746 0 211 0 200 0 3285 0 4055 0 CFG_VIN2A_D6_OUT vout2_d17
A10 vin2a_d7 2213 0 678 0 666 0 3552 0 4272 0 CFG_VIN2A_D7_OUT vout2_d16
B10 vin2a_d8 2268 0 733 0 721 0 3607 0 4277 0 CFG_VIN2A_D8_OUT vout2_d15
E10 vin2a_d9 2170 0 635 0 623 0 3509 0 4379 0 CFG_VIN2A_D9_OUT vout2_d14
B7 vin2a_de0 2102 0 568 0 556 0 3841 0 4611 0 CFG_VIN2A_DE0_OUT vout2_de
C7 vin2a_fld0 0 983 1398 1185 1385 1202 0 994 0 994 CFG_VIN2A_FLD0_OUT vout2_clk
E8 vin2a_hsync0 2482 0 974 0 936 0 4021 0 4891 0 CFG_VIN2A_HSYNC0_OUT vout2_hsync
B8 vin2a_vsync0 2296 0 784 0 750 0 3935 0 4805 0 CFG_VIN2A_VSYNC0_OUT vout2_vsync

Manual IO Timings Modes must be used to ensure some IO timings for VOUT3. See Table 5-29, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-46, Manual Functions Mapping for DSS VOUT3 for a definition of the Manual modes.

Table 5-46 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-46 Manual Functions Mapping for DSS VOUT3

BALL BALL NAME VOUT3_MANUAL1 VOUT3_MANUAL4 VOUT3_MANUAL5 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 3
M1 gpmc_a0 2395 0 3909 0 4779 0 CFG_GPMC_A0_OUT vout3_d16
M2 gpmc_a1 2412 0 3957 0 4827 0 CFG_GPMC_A1_OUT vout3_d17
J2 gpmc_a10 2473 0 3980 0 4850 0 CFG_GPMC_A10_OUT vout3_de
L3 gpmc_a11 2906 0 4253 0 5123 0 CFG_GPMC_A11_OUT vout3_fld
L2 gpmc_a2 2360 0 3873 0 4743 0 CFG_GPMC_A2_OUT vout3_d18
L1 gpmc_a3 2391 0 4112 0 4982 0 CFG_GPMC_A3_OUT vout3_d19
K3 gpmc_a4 2626 0 4336 0 5206 0 CFG_GPMC_A4_OUT vout3_d20
K2 gpmc_a5 2338 0 3840 0 4710 0 CFG_GPMC_A5_OUT vout3_d21
J1 gpmc_a6 2374 0 3913 0 4783 0 CFG_GPMC_A6_OUT vout3_d22
K1 gpmc_a7 2432 0 3947 0 4817 0 CFG_GPMC_A7_OUT vout3_d23
K4 gpmc_a8 3155 0 4309 105 5179 105 CFG_GPMC_A8_OUT vout3_hsync
H1 gpmc_a9 2309 0 3842 0 4712 0 CFG_GPMC_A9_OUT vout3_vsync
F1 gpmc_ad0 2360 0 3652 0 4522 0 CFG_GPMC_AD0_OUT vout3_d0
E2 gpmc_ad1 2420 0 3762 0 4632 0 CFG_GPMC_AD1_OUT vout3_d1
A2 gpmc_ad10 2235 0 3456 0 4326 0 CFG_GPMC_AD10_OUT vout3_d10
B3 gpmc_ad11 2253 0 3584 0 4454 0 CFG_GPMC_AD11_OUT vout3_d11
C3 gpmc_ad12 1949 427 3589 0 4459 0 CFG_GPMC_AD12_OUT vout3_d12
C4 gpmc_ad13 2318 0 3547 0 4417 0 CFG_GPMC_AD13_OUT vout3_d13
A3 gpmc_ad14 2123 0 3302 0 4172 0 CFG_GPMC_AD14_OUT vout3_d14
B4 gpmc_ad15 2195 29 3532 0 4402 0 CFG_GPMC_AD15_OUT vout3_d15
E1 gpmc_ad2 2617 0 3859 0 4729 0 CFG_GPMC_AD2_OUT vout3_d2
C1 gpmc_ad3 2350 0 3590 0 4460 0 CFG_GPMC_AD3_OUT vout3_d3
D1 gpmc_ad4 2324 0 3534 0 4404 0 CFG_GPMC_AD4_OUT vout3_d4
D2 gpmc_ad5 2371 0 3609 0 4479 0 CFG_GPMC_AD5_OUT vout3_d5
B1 gpmc_ad6 2231 0 3416 0 4286 0 CFG_GPMC_AD6_OUT vout3_d6
B2 gpmc_ad7 2440 0 3661 0 4531 0 CFG_GPMC_AD7_OUT vout3_d7
C2 gpmc_ad8 2479 0 3714 0 4584 0 CFG_GPMC_AD8_OUT vout3_d8
D3 gpmc_ad9 2355 0 3593 0 4463 0 CFG_GPMC_AD9_OUT vout3_d9
G3 gpmc_cs3 0 641 0 905 0 905 CFG_GPMC_CS3_OUT vout3_clk