The DRV870xD-Q1 device is controlled using a configurable input interface. The Logic Tables section provides the half-bridge operation states. These tables do not consider the current control built into the DRV870xD-Q1 device. The logic operation set by the MODE pin is latched on power-up or when exiting sleep mode. Figure 31 shows the direction of the flow of current through the load when it is connected between the SH pin and GND, and between the SH pin and VM.