SLVSC40H June   2013  – May 2020 DRV8711

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Indexer Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Motor Drivers
      2. 7.3.2  Direct PWM Input Mode
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Current Regulation
      5. 7.3.5  Decay Modes
      6. 7.3.6  Blanking Time
      7. 7.3.7  Predrivers
      8. 7.3.8  Configuring Predrivers
      9. 7.3.9  External FET Selection
      10. 7.3.10 Stall Detection
        1. 7.3.10.1 Internal Stall Detection
        2. 7.3.10.2 External Stall Detection
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 Overcurrent Protection (OCP)
        2. 7.3.11.2 Predriver Fault
        3. 7.3.11.3 Thermal Shutdown (TSD)
        4. 7.3.11.4 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 RESET and SLEEPn Operation
      2. 7.4.2 Microstepping Drive Current
    5. 7.5 Programming
      1. 7.5.1 Serial Data Format
    6. 7.6 Register Maps
      1. 7.6.1 Control Registers
      2. 7.6.2 CTRL Register (Address = 0x00)
      3. 7.6.3 TORQUE Register (Address = 0x01)
      4. 7.6.4 OFF Register (Address = 0x02)
      5. 7.6.5 BLANK Register (Address = 0x03)
      6. 7.6.6 DECAY Register (Address = 0x04)
      7. 7.6.7 STALL Register (Address = 0x05)
      8. 7.6.8 DRIVE Register (Address = 0x06)
      9. 7.6.9 STATUS Register (Address = 0x07)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Sense Resistor
      2. 8.1.2 Optional Series Gate Resistor
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Set Step Rate
        2. 8.2.2.2 Calculate Current Regulation
        3. 8.2.2.3 Support External FETs
        4. 8.2.2.4 Pick Decay Mode
        5. 8.2.2.5 Config Stall Detection
        6. 8.2.2.6 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 Decay Modes

During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 9, Item 1. The current flow direction shown indicates positive current flow in the step table below.

Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay.

In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. The opposite FETs are turned on; as the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 9, item 2.

In slow decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge. This is shown in Figure 9, Item 3.

DRV8711 dec_mod_SLVSC40.gifFigure 9. Decay Modes

The DRV8711 supports fast decay and slow decay modes in both indexer and direct PWM modes. In addition, in indexer mode only, it supports fixed mixed decay and auto-mixed decay modes. Decay mode is selected by the DECMOD bits in the DECAY register.

Mixed decay mode begins as fast decay, but after a programmable period of time (set by the TDECAY bits in the DECAY register) switches to slow decay mode for the remainder of the fixed off time. Even if mixed decay is selected, if the current is increasing or remaining the same (per the step table), then slow decay is used.

Auto-mixed decay mode samples the current level at the end of the blanking time, and if the current is above the Itrip threshold, immediately changes the H-bridge to fast decay. During fast decay, the (negative) current is monitored, and when it falls below the Itrip threshold (and another blanking time has passed), the bridge is switched to slow decay. Once the fixed off time expires, a new cycle is started.

If the bridge is turned on and at the end of TBLANK the current is below the Itrip threshold, the bridge remains on until the current reaches Itrip. Then slow decay is entered for the fixed off time, and a new cycle begins.

See Figure 10 and Figure 11.

The upper waveform shows the behavior if I < Itrip at the end of tBLANK. At slow motor speeds, where back EMF is not significant, the current increase during the ON phase is the same magnitude as the current decrease in fast decay, because both times are controlled by tBLANK, and the rate of change is the same (full VM is applied to the load inductance in both cases, but in opposite directions). In this case, the current will gradually be driven down until the peak current is just hitting Itrip at the end of the blanking time, after which some cycles will be slow decay, and some will be mixed decay.

DRV8711 dec_mod_tim_dia_1_SLVSC40.gifFigure 10. I < Itrip at the End of tBLANK

If the Itrip level changes during a PWM cycle (in response to a step command to the indexer), the current cycle is immediately terminated, and a new cycle is begun. Refer to the drawing below.

If the Itrip level has increased, the H-bridge will immediately turn on; if the Itrip level has decreased, fast decay mode is begun immediately. The top waveform shows what happens when the Itrip threshold decreases during a PWM cycle. The lower Itrip level results in the current being above the Itrip threshold at the end of tBLANK on the following cycle. Fast decay is entered until the current is driven below the Itrip threshold.

DRV8711 dec_mod_tim_dia_2_SLVSC40.gifFigure 11. Itrip Level Changing During a PWM Cycle

To accurately detect zero current, an internal offset has been intentionally placed in the zero current detection circuit. If an external filter is placed on the current sense resistor to the xISENN and xISENP pins, symmetry must be maintained. This means that any resistance between the bottom of the RISENSE resistor and xISENN must be matched by the same resistor value (1% tolerance) between the top of the RISENSE resistor and xISENP. Ensure a maximum resistance of 500 Ω. The capacitor value should be chosen such that the RC time constant is between 50 ns and 60 ns. Any external filtering on these pins is optional and not required for operation.

DRV8711 resistance2_slvsc40.gifFigure 12. Optional Filtering Between RISENSE and xINSENx