SLVSET1 August 2018 DRV8873
PRODUCTION DATA.
Table 18 lists the memory-mapped registers for the device. All register addresses not listed in Table 18 should be considered as reserved locations and the register contents should not be modified.
Register
Name |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Access
Type |
Address |
---|---|---|---|---|---|---|---|---|---|---|
FAULT Status | RSVD | FAULT | OTW | UVLO | CPUV | OCP | TSD | OLD | R | 0x00 |
DIAG Status | OL1 | OL2 | ITRIP1 | ITRIP2 | OCP_H1 | OCP_L1 | OCP_H2 | OCP_L2 | R | 0x01 |
IC1 Control | TOFF | SPI_IN | SR | MODE | RW | 0x02 | ||||
IC2 Control | ITRIP_REP | TSD_MODE | OTW_REP | DIS_CPUV | OCP_TRETRY | OCP_MODE | RW | 0x03 | ||
IC3 Control | CLR_FLT | LOCK | OUT1_DIS | OUT2_DIS | EN_IN1 | PH_IN2 | RW | 0x04 | ||
IC4 Control | RSVD | EN_OLP | OLP_DLY | EN_OLA | ITRIP_LVL | DIS_ITRIP | RW | 0x05 |
Complex bit access types are encoded to fit into small table cells. Table 19 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |