SLVSDS7B August 2019 – November 2019 DRV8876
An analog current limit circuit on each MOSFET limits the peak current out of the device even in hard short circuit events.
If the output current exceeds the overcurrent threshold, IOCP, for longer than tOCP, all MOSFETs in the H-bridge will be disabled and the nFAULT pin driven low. The overcurrent response can be configured through the IMODE pin as shown in Table 6.
In automatic retry mode, the MOSFETs will be disabled and nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the state of the EN/IN1 and PH/IN2 pins. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes.
In latched off mode, the MOSFETs will remain disabled and nFAULT pin driven low until the device is reset through either the nSLEEP pin or by removing the VM power supply.
In Independent Half-Bridge Control Mode (PMODE = Hi-Z), the OCP behavior is slightly modified. If an overcurrent event is detected, only the corresponding half-bridge will be disabled and the nFAULT pin driven low. The other half-bridge will continue normal operation. This allows for the device to manage independent fault events when driving independent loads. If an overcurrent event is detected in both half-bridges, both half-bridges will be disabled and the nFAULT pin driven low. In automatic retry mode, both half-bridges share the same overcurrent retry timer. If an overcurrent event occurs first in one half-bridge and then later in the secondary half-bridge, but before tRETRY has expired, the retry timer for the first half-bridge will be reset to tRETRY and both half-bridges will enable again after the retry timer expires.