SLVSD18C June 2015 – August 2017 DRV8880
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The DRV8880 is an integrated motor driver solution for bipolar stepper motors. The device integrates two NMOS H-bridges, current regulation circuitry, and a microstepping indexer. The DRV8880 can be powered with a supply voltage between 6.5 and 45 V, and is capable of providing an output current up to 2.5 A peak current, 2.0 A full-scale current, or 1.4 A rms current. Actual operable full-scale and rms current will depend on ambient temperature, supply voltage, and PCB ground plane size. Between VM = 6.4 V and VM = 4.9 V the H-bridge outputs are shut down, but the internal logic remains active in order to prevent missed steps.
A simple STEP/DIR interface allows easy interfacing to the controller circuit. The internal indexer is able to execute high-accuracy microstepping without requiring the processor to control the current level. The indexer is capable of full step and half step as well as microstepping to 1/4, 1/8, and 1/16. In addition to the standard half stepping mode, a non-circular 1/2-stepping mode is avaialble for increased torque output at higher motor rpm.
The current regulation is highly configurable, with several decay modes of operation. The decay mode can be selected as a fixed slow, slow/mixed, mixed, slow/fast, or fast decay. The slow/mixed decay mode uses slow decay on increasing steps and mixed decay on decreasing steps. Similarly, the slow/fast decay mode uses slow decay on increasing steps and fast decay on decreasing steps.
In addition, an AutoTune mode can be used which automatically adjusts the decay setting to minimize current ripple while still reacting quickly to step changes. This feature greatly simplifies stepper driver integration into a motor drive system.
The PWM off-time, tOFF, can be adjusted to 10, 20, or 30 µs.
An adaptive blanking time feature automatically scales the minimum drive time with output current. This helps alleviate zero-crossing distortion by limiting the drive time at low-current steps.
A torque DAC feature allows the controller to scale the output current without needing to scale the analog reference voltage input VREF. The torque DAC is accessed using digital input pins. This allows the controller to save power by decreasing the current consumption when not required.
A low-power sleep mode is included which allows the system to save power when not driving the motor.
Table 1 lists the recommended values of the external components.
COMPONENT | PIN 1 | PIN 2 | RECOMMENDED |
---|---|---|---|
CVM1 | VM | GND | 0.1-µF ceramic capacitor rated for VM per VM pin |
CVM1 | VM | GND | Bulk electrolytic capacitor rated for VM, recommended value is 100 µF, see Bulk Capacitance Sizing |
CVCP | VCP | VM | 16-V, 0.47-µF ceramic capacitor |
CSW | CPH | CPL | 0.1-µF X7R capacitor rated for VM |
CV3P3 | V3P3 | GND | 6.3-V, 0.47-µF ceramic capacitor |
RnFAULT | VMCU (1) | nFAULT | > 5 kΩ pullup |
RAISEN | AISEN | GND | Sense resistor, see Sense Resistor |
RBISEN | BISEN | GND |
Stepper motor drivers can be classified using three different numbers to describe the output current: peak, rms, and full-scale.
The peak current in a stepper driver is limited by the overcurrent protection trip threshold IOCP. The peak current describes any transient duration current pulse, for example when charging capacitance, when the overall duty cycle is very low. In general the minimum value of IOCP specifies the peak current rating of the stepper motor driver. For the DRV8880, the peak current rating is 2.5 A per bridge.
The rms (average) current is determined by the thermal considerations of the IC. The rms current is calculated based on the RDS(ON), rise and fall time, PWM frequency, device quiescent current, and package thermal performance in a typical system at 25°C. The real operating rms current may be higher or lower depending on heatsinking and ambient temperature. For the DRV8880, the rms current rating is 1.4 A per bridge.
The full-scale current describes the top of the sinusoid current waveform while microstepping. Since the sineusoid amplitude is related to the rms current, the full-scale current is also determined by the thermal considerations of the IC. The full-scale current rating is approximately √2 × Irms. The full-scale current is set by VREF, the sense resistor, and Torque DAC when configuring the DRV8880 , see Current Regulation for details. For the DRV8880, the full-scale current rating is 2.0 A per bridge.
The DRV8880 contains drivers for two full H-bridges. A block diagram of the circuitry is shown in Figure 13.
Built-in indexer logic in the DRV8880 allows a number of different stepping configurations. The Mx pins are used to configure the stepping format as shown in Table 2.
M1 | M0 | STEP MODE |
---|---|---|
0 | 0 | Full step (2-phase excitation) with 71% current |
0 | 1 | Non-circular 1/2 step |
1 | 0 | 1/2 step |
1 | 1 | 1/4 step |
0 | Z | 1/8 step |
1 | Z | 1/16 step |
Z | 0 | Reserved |
Z | 1 | Reserved |
Z | Z | Reserved |
Table 3 shows the relative current and step directions for full-step through 1/16-step operation. The AOUT current is the sine of the electrical angle; BOUT current is the cosine of the electrical angle. Positive current is defined as current flowing from xOUT1 to xOUT2 while driving.
At each rising edge of the STEP input the indexer travels to the next state in the table. The direction is shown with the DIR pin logic high. If the DIR pin is logic low, the sequence is reversed.
Note that if the step mode is changed while stepping, the indexer will advance to the next valid state for the new MODE setting at the rising edge of STEP.
The home state is an electrical angle of 45°. This state is entered after power-up, after exiting logic undervoltage lockout, or after exiting sleep mode. This is shown in Table 3 with the highlighted row.
FULL STEP | 1/2 STEP | 1/4 STEP | 1/8 STEP | 1/16 STEP | ELECTRICAL ANGLE (°) | AOUT CURRENT (% full-scale) |
BOUT CURRENT (% full-scale) |
---|---|---|---|---|---|---|---|
1 | 1 | 1 | 1 | 0.000° | 0% | 100% | |
2 | 5.625° | 10% | 100% | ||||
2 | 3 | 11.250° | 20% | 98% | |||
4 | 16.875° | 29% | 96% | ||||
2 | 3 | 5 | 22.500° | 38% | 92% | ||
6 | 28.125° | 47% | 88% | ||||
4 | 7 | 33.750° | 56% | 83% | |||
8 | 39.375° | 63% | 77% | ||||
1 | 2 | 3 | 5 | 9 | 45.000° | 71% | 71% |
10 | 50.625° | 77% | 63% | ||||
6 | 11 | 56.250° | 83% | 56% | |||
12 | 61.875° | 88% | 47% | ||||
4 | 7 | 13 | 67.500° | 92% | 38% | ||
14 | 73.125° | 96% | 29% | ||||
8 | 15 | 78.750° | 98% | 20% | |||
16 | 84.375° | 100% | 10% | ||||
3 | 5 | 9 | 17 | 90.000° | 100% | 0% | |
18 | 95.625° | 100% | –10% | ||||
10 | 19 | 101.250° | 98% | –20% | |||
20 | 106.875° | 96% | –29% | ||||
6 | 11 | 21 | 112.500° | 92% | –38% | ||
22 | 118.125° | 88% | –47% | ||||
12 | 23 | 123.750° | 83% | –56% | |||
24 | 129.375° | 77% | –63% | ||||
2 | 4 | 7 | 13 | 25 | 135.000° | 71% | –71% |
26 | 140.625° | 63% | –77% | ||||
14 | 27 | 146.250° | 56% | –83% | |||
28 | 151.875° | 47% | –88% | ||||
8 | 15 | 29 | 157.500° | 38% | –92% | ||
30 | 163.125° | 29% | –96% | ||||
16 | 31 | 168.750° | 20% | –98% | |||
32 | 174.375° | 10% | –100% | ||||
5 | 9 | 17 | 33 | 180.000° | 0% | –100% | |
34 | 185.625° | –10% | –100% | ||||
18 | 35 | 191.250° | –20% | –98% | |||
36 | 196.875° | –29% | –96% | ||||
10 | 19 | 37 | 202.500° | –38% | –92% | ||
38 | 208.125° | –47% | –88% | ||||
20 | 39 | 213.750° | –56% | –83% | |||
40 | 219.375° | –63% | –77% | ||||
3 | 6 | 11 | 21 | 41 | 225.000° | –71% | –71% |
42 | 230.625° | –77% | –63% | ||||
22 | 43 | 236.250° | –83% | –56% | |||
44 | 241.875° | –88% | –47% | ||||
12 | 23 | 45 | 247.500° | –92% | –38% | ||
46 | 253.125° | –96% | –29% | ||||
24 | 47 | 258.750° | –98% | –20% | |||
48 | 264.375° | –100% | –10% | ||||
7 | 13 | 25 | 49 | 270.000° | –100% | 0% | |
50 | 275.625° | –100% | 10% | ||||
26 | 51 | 281.250° | –98% | 20% | |||
52 | 286.875° | –96% | 29% | ||||
14 | 27 | 53 | 292.500° | –92% | 38% | ||
54 | 298.125° | –88% | 47% | ||||
28 | 55 | 303.750° | –83% | 56% | |||
56 | 309.375° | –77% | 63% | ||||
4 | 8 | 15 | 29 | 57 | 315.000° | –71% | 71% |
58 | 320.625° | –63% | 77% | ||||
30 | 59 | 326.250° | –56% | 83% | |||
60 | 331.875° | –47% | 88% | ||||
16 | 31 | 61 | 337.500° | –38% | 92% | ||
62 | 343.125° | –29% | 96% | ||||
32 | 63 | 348.750° | –20% | 98% | |||
64 | 354.375° | –10% | 100% | ||||
1 | 1 | 1 | 1 | 360.000° | 0% | 100% |
Non-circular 1/2–step operation is shown in Table 4. This stepping mode consumes more power than circular 1/2-step operation, but provides a higher torque at high motor rpm.
NON-CIRCULAR 1/2 STEP | ELECTRICAL ANGLE (°) |
AOUT CURRENT (% FULL-SCALE) |
BOUT CURRENT (% FULL-SCALE) |
---|---|---|---|
1 | 0° | 0 | 100 |
2 | 45° | 100 | 100 |
3 | 90° | 100 | 0 |
4 | 135° | 100 | -100 |
5 | 180° | 0 | -100 |
6 | 225° | –100 | -100 |
7 | 270° | –100 | 0 |
8 | 315° | –100 | 100 |
The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage, inductance of the winding, and the magnitude of the back EMF present. After the current hits the current chopping threshold, the bridge enters a decay mode for a fixed period of time to decrease the current, which is configurable between 10 and 30 µs through the tri-level input TOFF. After the off time expires, the bridge is re-enabled, starting another PWM cycle.
TOFF | OFF-TIME tOFF |
---|---|
0 | 20 µs |
1 | 30 µs |
Z | 10 µs |
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pin with a reference voltage. To generate the reference voltage for the current chopping comparator, the output of a sine lookup table is applied to a sine-weighted DAC, whose full-scale output voltage is set by VREF. This voltage is attenuated by a factor of Av. In addition, the TRQx pins further scale the reference.
The full-scale (100%) chopping current is calculated as follows:
The TRQx pins are the inputs to a Torque DAC used to scale the output current. The current scalar value for different inputs is shown below.
TRQ1 | TRQ0 | CURRENT SCALAR (TRQ) | EFFECTIVE ATTENUATION |
---|---|---|---|
1 | 1 | 25% | 26.4 V/V |
1 | 0 | 50% | 13.2 V/V |
0 | 1 | 75% | 8.8 V/V |
0 | 0 | 100% | 6.6 V/V |
Table 7 gives the xISEN trip voltage at a given DAC code and TRQ[1:0] setting for 1/16 step mode. In this table, VREF = 3.3 V.
1/16 STEP (SINE DAC CODE) | TORQUE DAC TRQ[1:0] SETTING | |||
---|---|---|---|---|
00 – 100% | 01 – 75% | 10 – 50% | 11 – 25% | |
16 | 500.0 mV | 375.0 mV | 250.0 mV | 125.0 mV |
15 | 490.0 mV | 367.5 mV | 245.0 mV | 122.5 mV |
14 | 480.0 mV | 360.0 mV | 240.0 mV | 120.0 mV |
13 | 460.0 mV | 345.0 mV | 230.0 mV | 115.0 mV |
12 | 440.0 mV | 330.0 mV | 220.0 mV | 110.0 mV |
11 | 415.0 mV | 311.3 mV | 207.5 mV | 103.8 mV |
10 | 385.0 mV | 288.8 mV | 192.5 mV | 96.3 mV |
9 | 355.0 mV | 266.3 mV | 177.5 mV | 88.8 mV |
8 | 315.0 mV | 236.3 mV | 157.5 mV | 78.8 mV |
7 | 280.0 mV | 210.0 mV | 140.0 mV | 70.0 mV |
6 | 235.0 mV | 176.3 mV | 117.5 mV | 58.8 mV |
5 | 190.0 mV | 142.5 mV | 95.0 mV | 47.5 mV |
4 | 145.0 mV | 108.8 mV | 72.5 mV | 36.3 mV |
3 | 100.0 mV | 75.0 mV | 50.0 mV | 25.0 mV |
2 | 50.0 mV | 37.5 mV | 25.0 mV | 12.5 mV |
1 | 0.0 mV | 0.0 mV | 0.0 mV | 0.0 mV |
A fixed decay mode is selected by setting the tri-level DECAYx pins as shown in Table 8. Please note that if the ATE pin is logic high, the DECAYx pins are ignored and AutoTune is used.
DECAY1 | DECAY0 | INCREASING STEPS | DECREASING STEPS |
---|---|---|---|
0 | 0 | Slow Decay | Slow Decay |
0 | 1 | Slow Decay | Mixed Decay: 2 tBLANK |
1 | 0 | Slow Decay | Mixed Decay: 30% Fast |
1 | 1 | Mixed Decay: 30% Fast | Mixed Decay: 30% Fast |
0 | Z | Slow Decay | Mixed Decay: 60% Fast |
1 | Z | Slow Decay | Fast Decay |
Z | 0 | Mixed Decay: 1 tBLANK | Mixed Decay: 30% Fast |
Z | 1 | Mixed Decay: 60% Fast | Mixed Decay: 60% Fast |
Z | Z | Fast Decay | Fast Decay |
Increasing and decreasing current are defined in the chart below. For the Slow/Mixed decay mode, the decay mode is set as slow during increasing current steps and mixed decay during decreasing current steps. In full step mode, the increasing step decay mode is always used.
During slow decay, both of the low-side FETs of the H-bridge are turned on, allowing the current to be recirculated.
Slow decay exhibits the least current ripple of the decay modes for a given tOFF. However on decreasing current steps, slow decay will take a long time to settle to the new ITRIP level because the current decreases very slowly.
In cases where current is held for a long time (no input in the STEP pin) or at very low stepping speeds, slow decay may not properly regulate current because no back-EMF is present across the motor windings. In this state, motor current can rise very quickly, and may require a large off-time. In some cases this may cause a loss of current regulation, and a more aggressive decay mode is recommended.
Mixed decay begins as fast decay for a time, followed by slow decay for the remainder of tOFF. In this mode, mixed decay only occurs during decreasing current. Slow decay is used for increasing current.
This mode exhibits the same current ripple as slow decay for increasing current, since for increasing current, only slow decay is used. For decreasing current, the ripple is larger than slow decay, but smaller than fast decay. On decreasing current steps, mixed decay will settle to the new ITRIP level faster than slow decay.
In cases where current is held for a long time (no input in the STEP pin) or at very low stepping speeds, slow decay may not properly regulate current because no back-EMF is present across the motor windings. In this state, motor current can rise very quickly, and may require a large off-time. In some cases this may cause a loss of current regulation, and a more aggressive decay mode is recommended.
Mixed decay begins as fast decay for a time, followed by slow decay for the remainder of tOFF. In this mode, mixed decay occurs for both increasing and decreasing current steps.
This mode exhibits ripple larger than slow decay, but smaller than fast decay. On decreasing current steps, mixed decay will settle to the new ITRIP level faster than slow decay.
In cases where current is held for a long time (no input in the STEP pin) or at very low stepping speeds, slow decay may not properly regulate current because no back-EMF is present across the motor windings. In this state, motor current can rise very quickly, and requires an excessively large off-time. Increasing/decreasing mixed decay mode allows the current level to stay in regulation when no back-EMF is present across the motor windings.
During fast decay, the polarity of the H-bridge is reversed. The H-bridge will be turned off as current approaches zero in order to prevent current flow in the reverse direction. In this mode, fast decay only occurs during decreasing current. Slow decay is used for increasing current.
Fast decay exhibits the highest current ripple of the decay modes for a given tOFF. Transition time on decreasing current steps is much faster than slow decay since the current is allowed to decrease much faster.
During fast decay, the polarity of the H-bridge is reversed. The H-bridge will be turned off as current approaches zero in order to prevent current flow in the reverse direction.
Fast decay exhibits the highest current ripple of the decay modes for a given tOFF. Transition time on decreasing current steps is much faster than slow decay since the current is allowed to decrease much faster.
To enable the AutoTune mode, pull the ATE pin logic high. Ensure the DECAYx pins are logic low. The AutoTune mode is registered internally when exiting from sleep mode or the power-up sequence. The ATE pin can be shorted to V3P3 to pull it logic high for this purpose.
AutoTune greatly simplifies the decay mode selection by automatically configuring the decay mode between slow, mixed, and fast decay. In mixed decay, AutoTune dynamically adjusts the fast decay percentage of the total mixed decay time. This feature eliminates motor tuning by automatically determining the best decay setting that results in the lowest ripple for the motor.
The decay mode setting is optimized iteratively each PWM cycle. If the motor current overshoots the target trip level, then the decay mode becomes more aggressive (add fast decay percentage) on the next cycle in order to prevent regulation loss. If there is a long drive time to reach the target trip level, the decay mode becomes less aggressive (remove fast decay percentage) on the next cycle in order to operate with less ripple and more efficiently. On falling steps, AutoTune will automatically switch to fast decay in order to reach the next step quickly.
AutoTune will automatically adjust the decay scheme based on operating factors like:
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a period of time before enabling the current sense circuitry. Note that the blanking time also sets the minimum drive time of the PWM.
The blanking time is automatically scaled so that the drive time is reduced at lower current steps.
The time tBLANK is determined by the sine DAC code and the torque DAC setting. The timing information for tBLANK is given in Table 9.
SINE DAC CODE | TORQUE DAC TRQ[1:0] SETTING | |||
---|---|---|---|---|
00 – 100% | 01 – 75% | 10 – 50% | 11 – 25% | |
16 | 1.80 µs | 1.50 µs | 1.50 µs | 1.20 µs |
15 | 1.80 µs | 1.50 µs | 1.50 µs | 1.20 µs |
14 | 1.80 µs | 1.50 µs | 1.50 µs | 1.20 µs |
13 | 1.80 µs | 1.50 µs | 1.50 µs | 1.20 µs |
12 | 1.80 µs | 1.50 µs | 1.50 µs | 1.20 µs |
11 | 1.80 µs | 1.50 µs | 1.50 µs | 1.20 µs |
10 | 1.80 µs | 1.50 µs | 1.50 µs | 1.20 µs |
9 | 1.80 µs | 1.50 µs | 1.50 µs | 1.20 µs |
8 | 1.50 µs | 1.50 µs | 1.20 µs | 0.90 µs |
7 | 1.50 µs | 1.50 µs | 1.20 µs | 0.90 µs |
6 | 1.50 µs | 1.50 µs | 1.20 µs | 0.90 µs |
5 | 1.50 µs | 1.50 µs | 1.20 µs | 0.90 µs |
4 | 1.20 µs | 1.20 µs | 0.90 µs | 0.90 µs |
3 | 1.20 µs | 1.20 µs | 0.90 µs | 0.90 µs |
2 | 0.90 µs | 0.90 µs | 0.90 µs | 0.90 µs |
1 | 0.90 µs | 0.90 µs | 0.90 µs | 0.90 µs |
A charge pump is integrated in order to supply a high-side NMOS gate drive voltage. The charge pump requires a capacitor between the VM and VCP pins. Additionally a low-ESR ceramic capacitor is required between pins CPH and CPL.
An LDO regulator is integrated into the DRV8880. It can be used to provide the supply voltage for low-current devices. For proper operation, bypass V3P3 to GND using a ceramic capacitor.
The V3P3 output is nominally 3.3 V. When the V3P3 LDO current load exceeds 10 mA, the LDO will behave like a constant current source. The output voltage will drop significantly with currents greater than 10 mA.
If a digital input needs to be tied permanently high (that is, M or TOFF), it is preferable to tie the input to V3P3 instead of an external regulator. This will save power when VM is not applied or in sleep mode: V3P3 is disabled and current will not be flowing through the input pulldown resistors. For reference, logic level inputs have a typical pulldown of 100 kΩ, and tri-level inputs have a typical pulldown of 40 kΩ.
The diagram below gives the input structure for logic-level pins STEP, DIR, ENABLE, nSLEEP, TRQ0, TRQ1, and ATE:
Tri-level logic pins TOFF, M0, M1, DECAY0, and DECAY1 have the following structure:
The control pins and reference input pin can be driven within the recommended operating conditions without the VM power supply present, or when the device is in sleep mode.
Each control pin has a weak pulldown resistor to ground. TI recommends setting the inputs to a logic low when in sleep mode to minimize current through the pulldown resistors.
The DRV8880 is fully protected against undervoltage, charge pump undervoltage, overcurrent, and overtemperature events.
If at any time the voltage on the VM pin falls below the VM undervoltage lockout threshold voltage (VUVLO2), all FETs in the H-bridge will be disabled, the charge pump will be disabled, and the nFAULT pin will be driven low. Operation will resume when VM rises above the UVLO2 threshold. The nFAULT pin will be released after operation has resumed.
The indexer position is not reset by this fault even though the output drivers are disabled. The indexer position is maintained and internal logic remains active until VM falls below the logic undervoltage threshold (VUVLO1).
If at any time the voltage on the VM pin falls below the logic undervoltage threshold voltage (VUVLO1), the internal logic is reset, and the V3P3 regulator is disabled. Operation will resume when VM rises above the UVLO1 threshold. The nFAULT pin is logic low during this state since it is pulled low upon encountering VM undervoltage. Decreasing VM below this undervoltage threshold will reset the indexer position.
If at any time the voltage on the VCP pin falls below the charge pump undervoltage lockout threshold voltage, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Operation will resume when VCP rises above the CPUV threshold. The nFAULT pin will be released after operation has resumed.
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume. The nFAULT pin will be released after operation has resumed.
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than tOCP, all FETs in the H-bridge will be disabled and nFAULT will be driven low. In addition to this FET current limit, an overcurrent condition is also detected if the voltage at xISEN exceeds VOCP.
The overcurrent fault response can be set to either latched mode or retry mode:
In latched mode, operation will resume after the ENABLE pin is brought logic low for at least 1 μs to reset the output driver. The nFAULT pin will be released after ENABLE is returned logic high. Removing and re-applying VM or toggling nSLEEP will also reset the latched fault.
In retry mode, the driver will be re-enabled after the OCP retry period (tRETRY) has passed. nFAULT becomes high again after the retry time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes and nFAULT remains deasserted.
A microcontroller can retain control of the ENABLE pin while in retry mode if it is operated like an open-drain output. Many microcontrollers support this. When the DRV8880 is operating normally, configure the MCU GPIO as an input. In this state, the MCU can detect whenever nFAULT is pulled low. In order to disable the DRV8880 output, configure the GPIO output state as low, and then configure the GPIO as an output.
Alternatively, a logic-level FET may be used to create an open drain external to the MCU. In this case, an additional MCU GPIO may be required in order to monitor the nFAULT pin.
FAULT | CONDITION | ERROR REPORT | H-BRIDGE | CHARGE PUMP | INDEXER | V3P3 | RECOVERY |
---|---|---|---|---|---|---|---|
VM undervoltage (UVLO2) |
VM < VUVLO2
(max 6.4 V) |
nFAULT | Disabled | Disabled | Operating |
Operating |
VM > VUVLO2
(max 6.5 V) |
Logic undervoltage (UVLO1) |
VM < VUVLO2
(max 4.9 V) |
None | Disabled | Disabled | Disabled |
Operating |
VM > VUVLO2
(max 4.8 V) |
VCP undervoltage (CPUV) |
VCP < VCPUV
(typ VM + 1.8 V) |
nFAULT | Disabled | Operating | Operating |
Operating |
VCP > VCPUV
(typ VM + 1.9 V) |
Thermal Shutdown (TSD) |
TJ > TTSD
(min 150°C) |
nFAULT | Disabled | Operating | Operating |
Operating |
TJ < TTSD - THYS
(THYS typ 35°C) |
Overcurrent (OCP) |
IOUT > IOCP
(min 2.5 A) VxISEN > VOCP (min 0.9 V) |
nFAULT | Disabled | Operating | Operating |
Operating |
ENABLE -or- tRETRY |
The DRV8880 internal logic, indexer, and charge pump are operating unless the nSLEEP pin is brought logic low. In sleep mode the charge pump is disabled, the H-bridge FETs are disabled Hi-Z, and the V3P3 regulator is disabled. tSLEEP must elapse after a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8880 is brought out of sleep mode automatically if nSLEEP is brought logic high. tWAKE must elapse before the outputs change state after wake-up.
If the ENABLE pin is brought logic low, the H-bridge outputs are disabled, but the charge pump and internal logic will remian active. A rising edge on STEP will advance the indexer, but the outputs will not change state until ENABLE brought logic high.
When VM falls below the VM undervoltage lockout threshold VUVLO2, the output driver and charge pump are disabled, but the internal logic and V3P3 remain active. In this mode, STEP inputs will advance the indexer, but the outputs will remain disabled. If VM falls below the logic undervoltage threshold VUVLO1, the internal logic is reset and the indexer will lose position.
CONDITION | H-BRIDGE | CHARGE PUMP | INDEXER | V3P3 | |
---|---|---|---|---|---|
Operating | 6.5 V < VM < 45 V nSLEEP pin = 1 ENABLE pin = 1 |
Operating | Operating | Operating | Operating |
Disabled | 6.5 V < VM < 45 V nSLEEP pin = 1 ENABLE pin = 0 |
Disabled | Operating | Operating | Operating |
Sleep mode | 5.0 V < VM < 45 V nSLEEP pin = 0 |
Disabled | Disabled | Disabled | Disabled |
Fault encountered | VM undervoltage (UVLO2) | Disabled | Disabled | Operating | Operating |
Logic undervoltage (UVLO1) | Disabled | Disabled | Disabled | Operating | |
VCP undervoltage (CPUV) | Disabled | Operating | Operating | Operating | |
Thermal shutdown (TSD) | Disabled | Operating | Operating | Operating | |
Overcurrent (OCP) | Disabled | Operating | Operating | Operating |