SNLS456D March   2016  – October 2019 DS250DF410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Retimer Jitter Specifications
    7. 7.7  Timing Requirements, Retimer Specifications
    8. 7.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 7.9  Recommended SMBus Switching Characteristics (Slave Mode)
    10. 7.10 Recommended SMBus Switching Characteristics (Master Mode)
    11. 7.11 Recommended JTAG Switching Characteristics
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  Signal Detect
      3. 8.3.3  Continuous Time Linear Equalizer (CTLE)
      4. 8.3.4  Variable Gain Amplifier (VGA)
      5. 8.3.5  Cross-Point Switch
      6. 8.3.6  Decision Feedback Equalizer (DFE)
      7. 8.3.7  Clock and Data Recovery (CDR)
      8. 8.3.8  Calibration Clock
      9. 8.3.9  Differential Driver with FIR Filter
        1. 8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
        2. 8.3.9.2 Output Driver Polarity Inversion
      10. 8.3.10 Debug Features
        1. 8.3.10.1 Pattern Generator
        2. 8.3.10.2 Pattern Checker
        3. 8.3.10.3 Eye Opening Monitor
      11. 8.3.11 Interrupt Signals
      12. 8.3.12 JTAG Boundary Scan
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Front-Port Jitter Cleaning Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Cable Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Backplane and Mid-plane Applications
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6 Register Maps

Table 8. Global Registers

ADDRESS
(HEX)		 BITS DEFAULT
VALUE
(HEX)		 MODE EEPROM FIELD NAME DESCRIPTION
EF 7 0 R N SPARE
6 0 R N SPARE
5 0 R N SPARE
4 0 R N SPARE
3 1 R N CHAN_CONFIG_ID[3] TI device ID (Quad count).
DS250DF810: 0x0C
DS250DF410: 0x0E
2 1 R N CHAN_CONFIG_ID[2]
1 1 R N CHAN_CONFIG_ID[1]
0 0 R N CHAN_CONFIG_ID[0]
F0 7 0 R N VERSION[7] Version ID
6 0 R N VERSION[6]
5 1 R N VERSION[5]
4 1 R N VERSION[4]
3 0 R N VERSION[3]
2 0 R N VERSION[2]
1 1 R N VERSION[1]
0 0 R N VERSION[0]
F1 7 0 R N DEVICE_ID[7] Full device ID
6 0 R N DEVICE_ID[6]
5 0 R N DEVICE_ID[5]
4 1 R N DEVICE_ID[4]
3 0 R N DEVICE_ID[3]
2 0 R N DEVICE_ID[2]
1 0 R N DEVICE_ID[1]
0 0 R N DEVICE_ID[0]
F3 7 0 R N CHAN_VERSION[3] Digital Channel Version
6 0 R N CHAN_VERSION[2]
5 0 R N CHAN_VERSION[1]
4 0 R N CHAN_VERSION[0]
3 0 R N SHARE_VERSION[3] Digital Share Version
2 0 R N SHARE_VERSION[2]
1 0 R N SHARE_VERSION[1]
0 0 R N SHARE_VERSION[0]
FB 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 1 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
FC 7 0 RW N EN_CH7 Select channel 7 (DS250DF810 only)
6 0 RW N EN_CH6 Select channel 6 (DS250DF810 only)
5 0 RW N EN_CH5 Select channel 5 (DS250DF810 only)
4 0 RW N EN_CH4 Select channel 4 (DS250DF810 only)
3 0 RW N EN_CH3 Select channel 3
2 0 RW N EN_CH2 Select channel 2
1 0 RW N EN_CH1 Select channel 1
0 0 RW N EN_CH0 Select channel 0
FD 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
FE 7 0 R N VENDOR_ID[7] TI vendor ID
6 0 R N VENDOR_ID[6]
5 0 R N VENDOR_ID[5]
4 0 R N VENDOR_ID[4]
3 0 R N VENDOR_ID[3]
2 0 R N VENDOR_ID[2]
1 1 R N VENDOR_ID[1]
0 1 R N VENDOR_ID[0]
FF 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 1 RW N EN_SHARE_Q1 Select shared registers for quad 1 (DS250DF810 only)
4 0 RW N EN_SHARE_Q0 Select shared registers for quad 0
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N WRITE_ALL_CH Allows user to write to all channels as if they are the same, but only allows read back from the channel specified in 0xFC.
Note: EN_CH_SMB must be = 1 or else this function is invalid.
0 0 RW N EN_CH_SMB 1: Enables SMBUS access to the channels specified in Reg_0xFC
0: The shared registers are selected

Table 9. Shared Registers

ADDRESS
(HEX)		 BITS DEFAULT
VALUE
(HEX)		 MODE EEPROM FIELD
NAME		 DESCRIPTION
00 7 1 R N SMBUS_ADDR[3] SMBus Address
6 1 R N SMBUS_ADDR[2] Strapped 7-bit addres is 0x18 + SMBus_Addr[3:0]
5 0 R N SMBUS_ADDR[1]
4 0 R N SMBUS_ADDR[0]
3:0 0 R N RESERVED RESERVED
01 7 1 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 1 R N RESERVED RESERVED
4 1 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 1 R N RESERVED RESERVED
02 7:0 0 RW N RESERVED RESERVED
03 7:0 0 RW N RESERVED RESERVED
04 7 0 RW N RESERVED RESERVED
6 0 RWSC N RST_I2C_REGS 1: Reset shared registers. This bit is self-clearing.
0: Normal operation
5 0 RWSC N RST_I2C_MAS 1: Reset for SMBus/I2C Master. This bit is self-clearing.
0: Normal operation
4 0 RW N FRC_EEPRM_RD 1: Force EEPROM Configuration
0: Normal operation
3 1 RW Y RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
05 7 0 RW N DISAB_EEPRM_CFG 1: Disable Master Mode EEPROM configuration (if not started; this bit is not effective if EEPROM configuration is already started)
0: Normal operation
6:5 0 RW N RESERVED RESERVED
4 1 R N EEPROM_READ_DONE 1: SMBus Master mode EEPROM read complete
0: SMBus Master mode EEPROM read not started or not complete
3 0 RW N TEST0_AS_CAL_CLK_IN 1: Use TEST0 as the input for the 25MHz CAL_CLK instead of CAL_CLK_IN. This must be configured for quad0 only.
0: Normal operation. Use CAL_CLK_IN as the input for the 25MHz CAL_CLK.
2 0 RW Y CAL_CLK_INV_DIS 1: Disable the inversion of CAL_CLK_OUT
0: Normal operation. CAL_CLK_OUT is inverted with respect to CAL_CLK_IN.
1 0 RW Y RESERVED RESERVED
0 1 RW Y RESERVED RESERVED
06 7:0 0 RW N RESERVED RESERVED
08 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N INT_Q0C3 Interrupt from channel 3. For DS250DF810, this applies to the quad selected by Reg_0xFF[5:4].
2 0 R N INT_Q0C2 Interrupt from channel 2. For DS250DF810, this applies to the quad selected by Reg_0xFF[5:4].
1 0 R N INT_Q0C1 Interrupt from channel 1. For DS250DF810, this applies to the quad selected by Reg_0xFF[5:4].
0 0 R N INT_Q0C0 Interrupt from channel 0. For DS250DF810, this applies to the quad selected by Reg_0xFF[5:4].
0A 7:1 0 R Y RESERVED RESERVED
0 0 RW Y DIS_REFCLK_OUT 1: Disable CAL_CLK_OUT (high-Z)
0: Normal operation. Enable CAL_CLK_OUT
0B 7 0 RW N RESERVED RESERVED
6 0 R N REFCLK_DET 1: 25MHz clock detected on CAL_CLK_IN
0: No clock detected on CAL_CLK_IN
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N MR_REFCLK_DET_DIS 0: CAL_CLK_IN detection and status reporting enabled (default)
1: CAL_CLK_IN detection disabled
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0C 7:0 0 RW N RESERVED RESERVED
0D 7:0 0 R N RESERVED RESERVED
0E 7:2 0 RW N RESERVED RESERVED
1:0 0 R N RESERVED RESERVED
0F 7:0 0 RW N RESERVED RESERVED
10 7 1 RW N RESERVED RESERVED
6 1 RW N RESERVED RESERVED
5 1 RW N RESERVED RESERVED
4 1 RW N RESERVED RESERVED
3 1 RW Y RESERVED RESERVED
2 1 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 1 RW Y RESERVED RESERVED
11 7 0 R N EECFG_CMPLT 11: Not valid
10: EEPROM load completed successfully
01: EEPROM load failed after 64 attempts
00: EEPROM load in progress
6 0 R N EECFG_FAIL
5 0 R N EECFG_ATMPT[5] Number of attempts made to load EEPROM image
4 0 R N EECFG_ATMPT[4]
3 0 R N EECFG_ATMPT[3]
2 0 R N EECFG_ATMPT[2]
1 0 R N EECFG_ATMPT[1]
0 0 R N EECFG_ATMPT[0]
12 7 1 RW N REG_I2C_FAST 1: EEPROM load uses Fast I2C Mode (400 kHz)
0: EEPROM load uses Standard I2C Mode (100 kHz)
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 1 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED

Table 10. Channel Registers, 0 to 39

ADDRESS
(HEX)		 BITS DEFAULT
VALUE
(HEX)		 MODE EEPROM FIELD NAME DESCRIPTION
00 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RST_CORE 1: Reset the 10M core clock domain. This is the main clock domain for all the state machines
0: Normal operation
2 0 RW N RST_REGS 1: Reset channel registers to power-up defaults.
0: Normal operation
1 0 RW N RST_VCO 1: Resets the CDR S2P clock domain, includes PPM counter, EOM counter.
0: Normal operation
0 0 RW N RST_REFCLK 1: Resets the 25MHz reference clock domain, includes PPM counter. Does not work if 25MHz clock is not present.
0: Normal operation
01 7 0 R N SIGDET Raw Signal Detect observation
6 0 R N POL_INV_DET Indicates PRBS checker detected polarity inversion in the locked data sequence.
5 0 R N CDR_LOCK_LOSS_INT 1: Indicates loss of CDR lock after having acquired it. Bit clears on read. Feature must be enabled with Reg_0x31[1]
4 0 R N PRBS_SEQ_DET[3] Indicates the pattern detected on the input serial stream
0xxx: No detect
1000: 7 bits PRBS sequence
1001: 9 bits PRBS sequence
1010: 11 bits PRBS sequence
1011: 15 bits PRBS sequence
1100: 23 bits PRBS sequence
1101: 31 bits PRBS sequence
1110: 58 bits PRBS sequence
1111: 63 bits PRBS sequence
3 0 R N PRBS_SEQ_DET[2]
2 0 R N PRBS_SEQ_DET[1]
1 0 R N PRBS_SEQ_DET[0]
0 0 R N SIG_DET_LOSS_INT Loss of signal indicator, set once signal is acquired and then lost. Clears on read. Feature must be enabled with reg_31[0]
02 7 0 R N CDR_STATUS[7] This register is used to read the status of internal signal.
Select what is observable on this bus using Reg_0x0C[7:4]
6 0 R N CDR_STATUS[6]
5 0 R N CDR_STATUS[5]
4 0 R N CDR_STATUS[4]
3 0 R N CDR_STATUS[3]
2 0 R N CDR_STATUS[2]
1 0 R N CDR_STATUS[1]
0 0 R N CDR_STATUS[0]
03 7 0 RW Y EQ_BST0[1] This register can be used to force an EQ boost setting if used in conjunction with channel Reg_0x2D[3].
6 0 RW Y EQ_BST0[0]
5 0 RW Y EQ_BST1[1]
4 0 RW Y EQ_BST1[0]
3 0 RW Y EQ_BST2[1]
2 0 RW Y EQ_BST2[0]
1 0 RW Y EQ_BST3[1]
0 0 RW Y EQ_BST3[0]
04 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
05 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
06 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
07 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
08 7 0 RW Y RESERVED RESERVED
6 1 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 1 RW Y RESERVED RESERVED
09 7 0 RW Y REG_VCO_CAP_OV Enable bit to override cap_cnt with value in Reg_0x0B[4:0]
6 0 RW Y REG_SET_CP_LVL_LPF_OV Enable bit to override lpf_dac_val with value in Reg_0x1F[4:0]
5 0 RW Y REG_BYPASS_PFD_OV 0: Normal operation.
4 0 RW Y REG_EN_FD_PD_VCO_PDIQ_OV Enable bit to override en_fd, pd_pd, pd_vco, pd_pdiq with Reg_0x1E[0], Reg_0x1E[2], Reg_0x1C[0], Reg_0x1C[1]
3 0 RW Y REG_EN_PD_CP_OV Enable bit to override pd_fd_cp and pd_pd_cp with value in Reg_0x1B[1:0]
2 0 RW Y REG_DIVSEL_OV Enable bit to override divsel with value in Reg_0x18[6:4]
1 0 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
0A 7 0 RW Y RESERVED RESERVED
6 0 RW Y REG_EN_IDAC_PD_CP_OV_
AND_REG_EN_IDAC_FD_CP_OV		 Enable bit to override phase detector charge pump settings with Reg_0x1C[7:5]
Enable bit to override frequency detector charge pump settings with Reg_0x1C[4:2]
5 0 RW Y REG_DAC_LPF_HIGH_PHASE_OV_
AND_REG_DAC_LPF_LOW_PHASE_OV		 Enable bit to loop filter comparator trip voltages with Reg_0x16[7:0]
4 0 RW Y RESERVED RESERVED
3 0 RW N REG_CDR_RESET_OV Enable CDR Reset override with Reg_0x0A[2]
2 0 RW N REG_CDR_RESET_SM CDR Reset override bit
1 0 RW N REG_CDR_LOCK_OV Enable CDR lock signal override with Reg_0x0A[0]
0 0 RW N REG_CDR_LOCK CDR lock signal override bit
0B 7 0 RW Y RESERVED RESERVED
6 1 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 1 RW Y RESERVED RESERVED
0C 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0D 7 1 RW N DES_PD 1: De-serializer (for PRBS checker) is powered down
0: De-serializer (for PRBS checker) is enabled
6 0 RW N RESERVED RESERVED
5 0 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0E 7 1 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 1 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 1 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
0F 7 0 RW N RESERVED RESERVED
6 1 RW N RESERVED RESERVED
5 1 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 1 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
10 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
11 7 0 RW Y EOM_SEL_VRANGE[1] Manually set the EOM vertical range, used with channel Reg_0x2C[6]:
00: ±100 mV
01: ±200 mV
10: ±300 mV
11: ±400 mV
6 0 RW Y EOM_SEL_VRANGE[0]
5 1 RW Y EOM_PD 1: Normal operation. Eye opening monitor (EOM) is automatically duty-cycled.
0: EOM is force-enabled
4 0 RW N RESERVED RESERVED
3 0 RW Y DFE_TAP2_POL Bit forces DFE tap 2 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
2 0 RW Y DFE_TAP3_POL Bit forces DFE tap 3 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
1 0 RW Y DFE_TAP4_POL Bit forces DFE tap 4 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
0 0 RW Y DFE_TAP5_POL Bit forces DFE tap 5 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
12 7 1 RW Y DFE_TAP1_POL Bit forces DFE tap 1 polarity
1: Negative, boosts by the specified tap weight
0: Positive, attenuates by the specified tap weight
6 0 RW N RESERVED RESERVED
5 0 RW Y RESERVED RESERVED
4 0 RW Y DFE_WT1[4] These bits force DFE tap 1 weight. Manual DFE operation is required for this to take effect by setting Reg_0x15[7]=1.
If Reg_0x15[7]=0, the value defined here is used as the initial DFE tap 1 weight during adaptation.
3 0 RW Y DFE_WT1[3]
2 0 RW Y DFE_WT1[2]
1 1 RW Y DFE_WT1[1]
0 1 RW Y DFE_WT1[0]
13 7 1 RW N EQ_PD_PEAKDETECT 1: Normal operation. Power down test mode.
0: Test mode.
6 0 RW Y EQ_PD_SD 1: Power down signal detect.
0: Normal operation. Enable signal detect.
5 1 RW Y EQ_HI_GAIN 1: Enable high DC gain mode in the equalizer
0: Enable low DC gain mode in the equalizer
(Refer to the Programming Guide for more details)
4 1 RW Y EQ_EN_DC_OFF 1: Normal operation.
0: Disable DC offset compensation.
3 0 RW Y RESERVED RESERVED
2 0 RW Y EQ_LIMIT_EN 1: Configures the final stage of the equalizer to be a limiting stage.
0: Normal operation, final stage of the equalizer is configured to be a non-limiting stage.
1 0 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
14 7 0 RW Y EQ_SD_PRESET 1: Forces signal detect HIGH, and force enables the channel. Should not be set if bit 6 is set.
0: Normal Operation.
6 0 RW Y EQ_SD_RESET 1: Forces signal detect LOW and force disables the channel. Should not be set if bit 7 is set.
0: Normal Operation.
5 0 RW Y EQ_REFA_SEL1 Controls the signal detect assert levels.
(Refer to the Programming Guide for more details)
4 0 RW Y EQ_REFA_SEL0
3 0 RW Y EQ_REFD_SEL1 Controls the signal detect de-assert levels.
(Refer to the Programming Guide for more details)
2 1 RW Y EQ_REFD_SEL0
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
15 7 0 RW Y DFE_FORCE_EN 1: Enables manual DFE tap settings
0: Normal operation
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 0 RW Y DRV_PD 1: Powers down the high speed driver
0: Normal operation
2 0 RW Y RESERVED RESERVED
1 0 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
16 7 0 RW Y RESERVED RESERVED
6 1 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 1 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
17 7 0 RW Y RESERVED RESERVED
6 0 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 1 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
18 7 0 RW N RESERVED RESERVED
6 1 RW Y PDIQ_SEL_DIV[2] These bits will force the divider setting if 0x09[2] is set.
000: Divide by 1
001: Divide by 2
010: Divide by 4
011: Divide by 8
100: Divide by 16
All other values are reserved.
5 0 RW Y PDIQ_SEL_DIV[1]
4 0 RW Y PDIQ_SEL_DIV[0]
3 0 RW N RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
19 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 0 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
1A 7 0 RW Y RESERVED RESERVED
6 1 RW Y RESERVED RESERVED
5 0 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 1 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
1B 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 1 RW Y CP_EN_CP_PD 1: Normal operation, phase detector charge pump enabled
0 1 RW Y CP_EN_CP_FD 1: Normal operation, frequency detector charge pump enabled
1C 7 1 RW Y EN_IDAC_PD_CP2 Phase detector charge pump setting. Override bit required for these bits to take effect
6 0 RW Y EN_IDAC_PD_CP1
5 0 RW Y EN_IDAC_PD_CP0
4 1 RW Y EN_IDAC_FD_CP2 Frequency detector charge pump setting. Override bit required for these bits to take effect
3 0 RW Y EN_IDAC_FD_CP1
2 0 RW Y EN_IDAC_FD_CP0
1 0 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
1D 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
1E 7 1 RW Y PFD_SEL_DATA_PRELCK[2] Output mode for when the CDR is not locked. For these values to take effect, Reg_0x09[5] must be set to 0, which is the default.
000: Raw Data
111: Mute (Default)
All other values are reserved. (Refer to the Programming Guide for more details)
6 1 RW Y PFD_SEL_DATA_PRELCK[1]
5 1 RW Y PFD_SEL_DATA_PRELCK[0]
4 0 RW N SER_EN 1: Enable serializer (used for PRBS Generator)
0: Normal operation. Disable serializer.
3 1 RW Y DFE_PD This bit must be cleared for the DFE to be functional in any adapt mode.
1: (Default) DFE disabled.
0: DFE enabled
2 0 RW Y PFD_PD_PD 1: Power down PFD phase detector.
0: Normal operation. Enable PFD phase detector.
1 0 RW Y EN_PARTIAL_DFE 1: Enable DFE taps 3-5. DFE_PD must also be set to 0.
0: (Default) Disable DFE taps 3-5.
0 1 RW Y PFD_EN_FD 1: Normal operation. Enable PFD frequency detector.
0: Disable PFD frequency detector.
1F 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 1 RW Y MR_LPF_AUTO_ADJST_EN 1: Normal operation. Allow LPF to tune to optimum value during fast-cap search routine.
0: Otherwise LPF value is determined by the Reg_0x9D.
2 0 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 1 RW Y RESERVED RESERVED
20 7 0 RW Y DFE_WT5[3] Bits force DFE tap 5 weight, manual DFE operation required to take effect by setting 0x15[7]=1.
6 0 RW Y DFE_WT5[2]
5 0 RW Y DFE_WT5[1]
4 0 RW Y DFE_WT5[0]
3 0 RW Y DFE_WT4[3] Bits force DFE tap 4 weight, manual DFE operation required to take effect by setting 0x15[7]=1.
2 0 RW Y DFE_WT4[2]
1 0 RW Y DFE_WT4[1]
0 0 RW Y DFE_WT4[0]
21 7 0 RW Y DFE_WT3[3] Bits force DFE tap 3 weight, manual DFE operation required to take effect by setting 0x15[7]=1.
6 0 RW Y DFE_WT3[2]
5 0 RW Y DFE_WT3[1]
4 0 RW Y DFE_WT3[0]
3 0 RW Y DFE_WT2[3] Bits force DFE tap 2 weight, manual DFE operation required to take effect by setting 0x15[7]=1.
2 0 RW Y DFE_WT2[2]
1 0 RW Y DFE_WT2[1]
0 0 RW Y DFE_WT2[0]
22 7 0 RW N EOM_OV 1: Override enable for EOM manual control
0: Normal operation
6 0 RW N EOM_SEL_RATE_OV 1: Override enable for EOM rate selection
0: Normal operation
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
23 7 0 RW N EOM_GET_HEO_VEO_OV 1: Override enable for manual control of the HEO/VEO trigger
0: Normal operation
6 1 RW Y DFE_OV 1: Normal operation; DFE must be enabled in Reg_0x1E[3].
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
24 7 0 RW N FAST_EOM 1: Enables fast EOM for full eye capture. In this mode the phase DAC and voltage DAC or the EOM are automatically incremented through a 64 x 64 matrix. Values for each point are stored in Reg_0x25 and Reg_0x26.
0: Normal operation.
6 0 R N DFE_EQ_ERROR_NO_LOCK DFE/CTLE SM quit due to loss of lock
5 0 R N GET_HEO_VEO_ERROR_NO_HITS get_heo_veo sees no hits at zero crossing
4 0 R N GET_HEO_VEO_ERROR_NO_OPENING get_heo_veo cannot see a vertical eye opening
3 0 RW N RESERVED RESERVED
2 0 RWSC N DFE_ADAPT 1: Manually start DFE adaption (self-clearing).
0: Normal operation.
1 0 R N EOM_GET_HEO_VEO 1: Manually triggers HEO/VEO measurement; feature must be enabled with Reg_0x23[7]; the HEO/VEO values are read from Reg_0x27, Reg_0x28
0 0 RWSC N EOM_START 1: Starts EOM counter, self-clearing
25 7 0 R N EOM_COUNT15 MSBs of EOM counter
6 0 R N EOM_COUNT14
5 0 R N EOM_COUNT13
4 0 R N EOM_COUNT12
3 0 R N EOM_COUNT11
2 0 R N EOM_COUNT10
1 0 R N EOM_COUNT9
0 0 R N EOM_COUNT8
26 7 0 R N EOM_COUNT7 LSBs of EOM counter
6 0 R N EOM_COUNT6
5 0 R N EOM_COUNT5
4 0 R N EOM_COUNT4
3 0 R N EOM_COUNT3
2 0 R N EOM_COUNT2
1 0 R N EOM_COUNT1
0 0 R N EOM_COUNT0
27 7 0 R N HEO7 HEO value, requires CDR to be locked for valid measurement
6 0 R N HEO6
5 0 R N HEO5
4 0 R N HEO4
3 0 R N HEO3
2 0 R N HEO2
1 0 R N HEO1
0 0 R N HEO0
28 7 0 R N VEO7 VEO value, requires CDR to be locked for valid measurement
6 0 R N VEO6
5 0 R N VEO5
4 0 R N VEO4
3 0 R N VEO3
2 0 R N VEO2
1 0 R N VEO1
0 0 R N VEO0
29 7 0 RW N RESERVED RESERVED
6 0 R N EOM_VRANGE_SETTING[1] Read the currently set Eye Monitor Voltage Range:
11 - +/-400mV
10 - +/- 300mV
01 - +/- 200mV
00 - +/- 100mV"
5 0 R N EOM_VRANGE_SETTING[0]
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 R N VEO[8] VEO MSB value
0 0 R N HEO[8] HEO MSB value
2A 7 0 RW Y EOM_TIMER_THR[3] The value of EOM_TIMER_THR[7:4] controls the amount of time the Eye Monitor samples each point in the eye.
(Refer to the Programming Guide for more details)
6 1 RW Y EOM_TIMER_THR[2]
5 0 RW Y EOM_TIMER_THR[1]
4 1 RW Y EOM_TIMER_THR[0]
3 1 RW Y VEO_MIN_REQ_HITS[3] Whenever the Eye Monitor is used to measure HEO and VEO, the data is sampled for some number of bits, set by Reg_0x2A[7:4]. This register sets the number of hits within that sample size that is required before the EOM will indicate a hit has occurred. This filtering only affects the VEO measurement.
2 0 RW Y VEO_MIN_REQ_HITS[2]
1 1 RW Y VEO_MIN_REQ_HITS[1]
0 0 RW Y VEO_MIN_REQ_HITS[0]
2B 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 1 RW Y EOM_MIN_REQ_HITS[3] Whenever the Eye Monitor is used to measure HEO and VEO, the data is sampled for some number of bits, set by Reg_0x2A[7:4]. This register sets the number of hits within that sample size that is required before the EOM will indicate a hit has occurred. This filtering only affects the HEO measurement.
2 0 RW Y EOM_MIN_REQ_HITS[2]
1 1 RW Y EOM_MIN_REQ_HITS[1]
0 0 RW Y EOM_MIN_REQ_HITS[0]
2C 7 1 RW N RELOAD_DFE_TAPS Causes DFE taps to load from last adapted values
6 1 RW Y VEO_SCALE 1: Normal operation. Scale VEO based on EOM vrange.
5 1 RW Y DFE_SM_FOM1 This register defines the Figure of Merit used when adapting the DFE:
00: not valid
01: SM uses only HEO
10: SM uses only VEO
11: SM uses both HEO and VEO
Additionally, if Reg_0x6E[6] is set to '1', the Alternate FOM is used. This bit takes precedence over DFE_SM_FOM
4 1 RW Y DFE_SM_FOM0
3 0 RW Y DFE_ADAPT_COUNTER[3] DFE look-beyond count.
2 1 RW Y DFE_ADAPT_COUNTER[2]
1 1 RW Y DFE_ADAPT_COUNTER[1]
0 0 RW Y DFE_ADAPT_COUNTER[0]
2D 7 0 RW Y RESERVED RESERVED
6 0 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 0 RW Y REG_EQ_BST_OV 1: Allow override control of the EQ setting by writing to Reg_0x03
0: Normal operation.
2 0 RW Y RESERVED RESERVED
1 0 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
2E 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 R N EQ_BST3_BIT2_TO_EQ Read-back of eq_BST3[2] driving the EQ
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N PRBS_PATTERN_SEL[2] MSB for the PRBS_PATTERN_SEL field. Lower bits are found on Reg_0x30[1:0]. Refer to the Reg_0x30 description on this table.
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
2F 7 0 RW Y RESERVED RESERVED
6 1 RW Y RATE[2] Configure PPM register and divider for a standard data rate.
(Refer to the Programming Guide for more details)
5 0 RW Y RATE[1]
4 1 RW Y RATE[0]
3 0 RW Y INDEX_OV If this bit is 1, then Reg_0x39 is to be used as 4-bit index to the [15:0] array of EQ settings. The EQ setting at that index is loaded to the EQ boost registers going to the analog and is used as the starting point for adaption.
2 1 RW Y EN_PPM_CHECK 1: (Default) Enable the PPM to be used as a qualifier when performing Lock Detect
0: Remove the PPM check as a lock qualifier.
1 0 RW Y RESERVED RESERVED
0 0 RWSC N CTLE_ADAPT 1: Re-starts CTLE adaptation, self-clearing
30 7 0 RW N FREEZE_PPM_CNT 1: Freeze the PPM counter to allow safe read asynchronously
6 0 RW Y EQ_SEARCH_OV_EN 1: Enables the EQ 'search" bit to be forced by Reg_0x13[2]
5 0 RW N EN_PATT_INV 1: Enable automatic pattern inversion of successive 16 bit words when using the "Fixed Pattern" generator option.
4 0 RW N RELOAD_PRBS_CHKR 1: Force reload of seed into PRBS checker LFSR without holding the checker in reset.
3 0 RW N PRBS_EN_DIG_CLK This bit enables the clock to operate the PRBS generator and/or the PRBS checher. Toggling this bit is the primary method to reset the PRBS pattern generator and PRBS checker.
2 0 RW N PRBS_PROGPATT_EN Enable a fixed data pattern output. Requires that serializer is enabled with Reg_0x1E[4]. PRBS generator and checker should be disabled, Reg_0x30[3]. The fixed data pattern is set by Reg_0x7C and Reg_0x97. Enable inversion of the pattern every 16 bits with Reg_0x30[5].
1 0 RW N PRBS_PATTERN_SEL[1] Selects the pattern output when using the PRBS generator. Requires the pattern generator to be configured properly. The MSB for the PRBS_PATTERN_SEL field is in Reg_0x2E[2].
Use Reg_0x30[3] to enable the PRBS generator.
000: 2^7-1 bits PRBS sequence
001: 2^9-1 bits PRBS sequence
010: 2^11-1 bits PRBS sequence
011: 2^15-1 bits PRBS sequence
100: 2^23-1 bits PRBS sequence
101: 2^31-1 bits PRBS sequence
110: 2^58-1 bits PRBS sequence
111: 2^63-1 bits PRBS sequence
0 0 RW N PRBS_PATTERN_SEL[0]
31 7 0 RW N PRBS_INT_EN 1: Enables interrupt for detection of PRBS errors. The PRBS checker must be properly configured for this feature to work.
6 0 RW Y ADAPT_MODE[1] 00: no adaption
01: adapt CTLE only
10: adapt CTLE until optimal, then DFE, then CTLE again
11: adapt CTLE until lock, then DFE, then EQ until optimal
Note: for ADAPT_MODE=2 or 3, the DFE must be enabled by setting Reg_0x1E[3]=0 and Reg_0x1E[1]=1.
(Refer to the Programming Guide for more details)
5 1 RW Y ADAPT_MODE[0]
4 0 RW Y EQ_SM_FOM[1] CTLE (EQ) adaption state machine figure of merit.
00: (Default) SM uses both HEO and VEO
01: SM uses HEO only
10: SM uses VEO only
11: SM uses both HEO and VEO
Additionally, if Reg_0x6E[7]=1, the Alternate FOM is used. Reg_0x6E[7] takes precedence over EQ_SM_FOM.
3 0 RW Y EQ_SM_FOM[0]
2 0 RW N RESERVED RESERVED
1 0 RW Y CDR_LOCK_LOSS_INT_EN Enable for CDR Lock Loss Interrupt. Observable in Reg_0x01[5]
0 0 RW Y SIGNAL_DET_LOSS_INT_EN Enable for Signal Detect Loss Interrupt. Observable in Reg_0x01[0]
32 7 0 RW Y HEO_INT_THRESH[3] These bits set the threshold for the HEO and VEO interrupt. Each threshold bit represents 8 counts of HEO or VEO.
6 0 RW Y HEO_INT_THRESH[2]
5 0 RW Y HEO_INT_THRESH[1]
4 1 RW Y HEO_INT_THRESH[0]
3 0 RW Y VEO_INT_THRESH[3]
2 0 RW Y VEO_INT_THRESH[2]
1 0 RW Y VEO_INT_THRESH[1]
0 1 RW Y VEO_INT_THRESH[0]
33 7 1 RW Y HEO_THRESH[3] In adapt mode 3, the register sets the minimum HEO and VEO required for CTLE adaption, before starting DFE adaption. This can be a max of 15.
6 0 RW Y HEO_THRESH[2]
5 0 RW Y HEO_THRESH[1]
4 0 RW Y HEO_THRESH[0]
3 1 RW Y VEO_THRESH[3]
2 0 RW Y VEO_THRESH[2]
1 0 RW Y VEO_THRESH[1]
0 0 RW Y VEO_THRESH[0]
34 7 0 R N PPM_ERR_RDY 1: Indicates that a PPM error count is read to be read from channel Reg_0x3B and Reg_0x3C
6 0 RW Y LOW_POWER_MODE_DISABLE By default, all blocks (except signal detect) power down after 100 ms after signal detect goes low. If set high, all blocks get powered on after the signal detect initially goes high.
5 1 RW Y LOCK_COUNTER[1] After achieving lock, the CDR continues to monitor the lock criteria. If the lock criteria fail, the lock is checked for a total of N number of times before declaring an out of lock condition, where N is set by this the value in these registers, with a max value of +3, for a total of 4. If during the N lock checks, lock is regained, then the lock condition is left HI, and the counter is reset back to zero.
4 1 RW Y LOCK_COUNTER[0]
3 1 RW Y DFE_MAX_TAP2_5[3] These four bits are used to set the maximum value by which DFE taps 2-5 are able to adapt with each subsequent adaptation. Same used for both polarities.
2 1 RW Y DFE_MAX_TAP2_5[2]
1 1 RW Y DFE_MAX_TAP2_5[1]
0 1 RW Y DFE_MAX_TAP2_5[0]
35 7 0 RW Y DATA_LOCK_PPM[1] Modifies the value of the PPM delta tolerance from channel Reg_0x64:
00 - ppm_delta[7:0] =1 x ppm_delta[7:0]
01 - ppm_delta[7:0] =1 x ppm_delta[7:0] + ppm_delta[3:1]
10 - ppm_delta[7:0] =2 x ppm_delta[7:0]
11 - ppm_delta[7:0] =2 x ppm_delta[7:0] + ppm_delta[3:1]
6 0 RW Y DATA_LOCK_PPM[0]
5 0 RW N GET_PPM_ERROR Get PPM error from PPM_COUNT - clears when done. Normally updates continuously, but can be manually triggered with read value from Reg_0x3B and Reg_0x3C
4 0 RW Y DFE_MAX_TAP1[4] Limits DFE tap 1 maximum magnitude.
3 1 RW Y DFE_MAX_TAP1[3]
2 1 RW Y DFE_MAX_TAP1[2]
1 1 RW Y DFE_MAX_TAP1[1]
0 1 RW Y DFE_MAX_TAP1[0]
36 7 0 RW N RESERVED RESERVED
6 0 RW Y HEO_VEO_INT_EN 1: Enable HEO/VEO interrupt capability
5 1 RW Y REF_MODE[1] 11: Normal Operation. Refererence mode 3.
4 1 RW Y REF_MODE[0]
3 0 RW N RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
37 7 0 R N CTLE_STATUS[7] Feature is reserved for future use
6 0 R N CTLE_STATUS[6]
5 0 R N CTLE_STATUS[5]
4 0 R N CTLE_STATUS[4]
3 0 R N CTLE_STATUS[3]
2 0 R N CTLE_STATUS[2]
1 0 R N CTLE_STATUS[1]
0 0 R N CTLE_STATUS[0]
38 7 0 R N DFE_STATUS[7] Feature is reserved for future use
6 0 R N DFE_STATUS[6]
5 0 R N DFE_STATUS[5]
4 0 R N DFE_STATUS[4]
3 0 R N DFE_STATUS[3]
2 0 R N DFE_STATUS[2]
1 0 R N DFE_STATUS[1]
0 0 R N DFE_STATUS[0]
39 7 0 RW N RESERVED RESERVED
6 1 RW Y MR_EOM_RATE[1] With eom_ov = 1, these bits control the Eye Monitor Rate:
11: Use for full rate, fastest
10: Use for 1/2 Rate
All other values are reserved
5 1 RW Y MR_EOM_RATE[0]
4 0 RW Y RESERVED RESERVED
3 0 RW Y START_INDEX[3] Start index for EQ adaptation
2 0 RW Y START_INDEX[2]
1 0 RW Y START_INDEX[1]
0 0 RW Y START_INDEX[0]

Table 11. Channel Registers, 3A to A9

ADDRESS
(Hex)		 BITS DEFAULT
VALUE
(Hex)		 MODE EEPROM FIELD NAME DESCRIPTION
3A 7 0 RW Y FIXED_EQ_BST0[1] During adaptation, if the divider setting is >2, then a fixed EQ setting from this register will be used. However, if channel Reg_0x6F[7] is enabled, then an EQ adaptation will be performed instead
6 0 RW Y FIXED_EQ_BST0[0]
5 0 RW Y FIXED_EQ_BST1[1]
4 0 RW Y FIXED_EQ_BST1[0]
3 0 RW Y FIXED_EQ_BST2[1]
2 0 RW Y FIXED_EQ_BST2[0]
1 0 RW Y FIXED_EQ_BST3[1]
0 0 RW Y FIXED_EQ_BST3[0]
3B 7 0 R N PPM_COUNT[15] PPM count MSB
6 0 R N PPM_COUNT[14]
5 0 R N PPM_COUNT[13]
4 0 R N PPM_COUNT[12]
3 0 R N PPM_COUNT[11]
2 0 R N PPM_COUNT[10]
1 0 R N PPM_COUNT[9]
0 0 R N PPM_COUNT[8]
3C 7 0 R N PPM_COUNT[7] PPM count LSB
6 0 R N PPM_COUNT[6]
5 0 R N PPM_COUNT[5]
4 0 R N PPM_COUNT[4]
3 0 R N PPM_COUNT[3]
2 0 R N PPM_COUNT[2]
1 0 R N PPM_COUNT[1]
0 0 R N PPM_COUNT[0]
3D 7 0 RW Y EN_FIR_CURSOR 1: Enable Pre- and Post-cursor FIR
0: Disable Pre- and Post-cursor FIR (lower power)
6 0 RW Y FIR_C0_SGN Main-cursor sign bit
0: positive
1: negative
5 0 RW Y RESERVED RESERVED
4 1 RW Y FIR_C0[4] Main-cursor magnitude
(Refer to the Programming Guide for more details)
3 1 RW Y FIR_C0[3]
2 0 RW Y FIR_C0[2]
1 1 RW Y FIR_C0[1]
0 0 RW Y FIR_C0[0]
3E 7 0 RW Y FIR_PD_TX
6 1 RW Y FIR_CN1_SGN Pre-cursor sign bit
1: negative
0: positive
5 0 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 0 RW Y FIR_CN1[3] Pre-cursor magnitude
(Refer to the Programming Guide for more details)
2 0 RW Y FIR_CN1[2]
1 0 RW Y FIR_CN1[1]
0 0 RW Y FIR_CN1[0]
3F 7 0 RW Y RESERVED RESERVED
6 1 RW Y FIR_CP1_SGN Post-cursor sign bit
1: negative
0: positive
5 0 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 0 RW Y FIR_CP1[3] Post-cursor magnitude
(Refer to the Programming Guide for more details)
2 0 RW Y FIR_CP1[2]
1 0 RW Y FIR_CP1[1]
0 0 RW Y FIR_CP1[0]
40 7 0 RW Y EQ_ARRAY_INDEX_0_BST0[1]
6 0 RW Y EQ_ARRAY_INDEX_0_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_0_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_0_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_0_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_0_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_0_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_0_BST3[0]
41 7 0 RW Y EQ_ARRAY_INDEX_1_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_1_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_1_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_1_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_1_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_1_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_1_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_1_BST3[0]
42 7 0 RW Y EQ_ARRAY_INDEX_2_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_2_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_2_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_2_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_2_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_2_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_2_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_2_BST3[0]
43 7 1 RW Y EQ_ARRAY_INDEX_3_BST0[1]
6 0 RW Y EQ_ARRAY_INDEX_3_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_3_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_3_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_3_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_3_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_3_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_3_BST3[0]
44 7 1 RW Y EQ_ARRAY_INDEX_4_BST0[1]
6 0 RW Y EQ_ARRAY_INDEX_4_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_4_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_4_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_4_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_4_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_4_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_4_BST3[0]
45 7 1 RW Y EQ_ARRAY_INDEX_5_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_5_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_5_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_5_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_5_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_5_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_5_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_5_BST3[0]
46 7 1 RW Y EQ_ARRAY_INDEX_6_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_6_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_6_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_6_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_6_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_6_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_6_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_6_BST3[0]
47 7 1 RW Y EQ_ARRAY_INDEX_7_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_7_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_7_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_7_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_7_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_7_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_7_BST3[1]
0 1 RW Y EQ_ARRAY_INDEX_7_BST3[0]
48 7 1 RW Y EQ_ARRAY_INDEX_8_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_8_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_8_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_8_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_8_BST2[1]
2 1 RW Y EQ_ARRAY_INDEX_8_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_8_BST3[1]
0 1 RW Y EQ_ARRAY_INDEX_8_BST3[0]
49 7 1 RW Y EQ_ARRAY_INDEX_9_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_9_BST0[0]
5 0 RW Y EQ_ARRAY_INDEX_9_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_9_BST1[0]
3 1 RW Y EQ_ARRAY_INDEX_9_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_9_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_9_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_9_BST3[0]
4A 7 1 RW Y EQ_ARRAY_INDEX_10_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_10_BST0[0]
5 1 RW Y EQ_ARRAY_INDEX_10_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_10_BST1[0]
3 1 RW Y EQ_ARRAY_INDEX_10_BST2[1]
2 0 RW Y EQ_ARRAY_INDEX_10_BST2[0]
1 1 RW Y EQ_ARRAY_INDEX_10_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_10_BST3[0]
4B 7 1 RW Y EQ_ARRAY_INDEX_11_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_11_BST0[0]
5 1 RW Y EQ_ARRAY_INDEX_11_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_11_BST1[0]
3 0 RW Y EQ_ARRAY_INDEX_11_BST2[1]
2 1 RW Y EQ_ARRAY_INDEX_11_BST2[0]
1 1 RW Y EQ_ARRAY_INDEX_11_BST3[1]
0 1 RW Y EQ_ARRAY_INDEX_11_BST3[0]
4C 7 1 RW Y EQ_ARRAY_INDEX_12_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_12_BST0[0]
5 1 RW Y EQ_ARRAY_INDEX_12_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_12_BST1[0]
3 1 RW Y EQ_ARRAY_INDEX_12_BST2[1]
2 1 RW Y EQ_ARRAY_INDEX_12_BST2[0]
1 0 RW Y EQ_ARRAY_INDEX_12_BST3[1]
0 1 RW Y EQ_ARRAY_INDEX_12_BST3[0]
4D 7 1 RW Y EQ_ARRAY_INDEX_13_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_13_BST0[0]
5 1 RW Y EQ_ARRAY_INDEX_13_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_13_BST1[0]
3 1 RW Y EQ_ARRAY_INDEX_13_BST2[1]
2 1 RW Y EQ_ARRAY_INDEX_13_BST2[0]
1 1 RW Y EQ_ARRAY_INDEX_13_BST3[1]
0 0 RW Y EQ_ARRAY_INDEX_13_BST3[0]
4E 7 1 RW Y EQ_ARRAY_INDEX_14_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_14_BST0[0]
5 1 RW Y EQ_ARRAY_INDEX_14_BST1[1]
4 0 RW Y EQ_ARRAY_INDEX_14_BST1[0]
3 1 RW Y EQ_ARRAY_INDEX_14_BST2[1]
2 1 RW Y EQ_ARRAY_INDEX_14_BST2[0]
1 1 RW Y EQ_ARRAY_INDEX_14_BST3[1]
0 1 RW Y EQ_ARRAY_INDEX_14_BST3[0]
4F 7 1 RW Y EQ_ARRAY_INDEX_15_BST0[1]
6 1 RW Y EQ_ARRAY_INDEX_15_BST0[0]
5 1 RW Y EQ_ARRAY_INDEX_15_BST1[1]
4 1 RW Y EQ_ARRAY_INDEX_15_BST1[0]
3 1 RW Y EQ_ARRAY_INDEX_15_BST2[1]
2 1 RW Y EQ_ARRAY_INDEX_15_BST2[0]
1 1 RW Y EQ_ARRAY_INDEX_15_BST3[1]
0 1 RW Y EQ_ARRAY_INDEX_15_BST3[0]
50 7 1 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 1 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
51 7 1 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 1 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
52 7 1 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 1 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
53 7 0 RW N RESERVED RESERVED
6 1 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 1 RW N RESERVED RESERVED
1 1 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
54 7 0 RW N RESERVED RESERVED
6 1 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 1 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 1 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
55 7 1 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 1 RW N RESERVED RESERVED
2 1 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
56 7 1 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 1 RW N RESERVED RESERVED
4 1 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
57 7 1 RW N RESERVED RESERVED
6 1 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 1 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
58 7 0 RW N RESERVED RESERVED
6 1 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 1 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 1 RW N RESERVED RESERVED
1 1 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
59 7 0 RW N RESERVED RESERVED
6 1 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 1 RW N RESERVED RESERVED
3 1 RW N RESERVED RESERVED
2 1 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
5A 7 0 RW N RESERVED RESERVED
6 1 RW N RESERVED RESERVED
5 1 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 1 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
5B 7 0 RW N RESERVED RESERVED
6 1 RW N RESERVED RESERVED
5 1 RW N RESERVED RESERVED
4 1 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 1 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
5C 7 1 RW N RESERVED RESERVED
6 1 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 1 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 1 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
5D 7 1 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 1 RW N RESERVED RESERVED
3 1 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
5E 7 1 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 1 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 1 RW N RESERVED RESERVED
1 1 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
5F 7 1 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 1 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 1 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 1 RW N RESERVED RESERVED
60 7 0 RW Y GRP0_OV_CNT[7] Group 0 count LSB
6 0 RW Y GRP0_OV_CNT[6]
5 0 RW Y GRP0_OV_CNT[5]
4 0 RW Y GRP0_OV_CNT[4]
3 0 RW Y GRP0_OV_CNT[3]
2 0 RW Y GRP0_OV_CNT[2]
1 0 RW Y GRP0_OV_CNT[1]
0 0 RW Y GRP0_OV_CNT[0]
61 7 0 RW Y CNT_DLTA_OV_0 Override enable for group 0 manual data rate selection
6 0 RW Y GRP0_OV_CNT[14] Group 0 count MSB
5 0 RW Y GRP0_OV_CNT[13]
4 0 RW Y GRP0_OV_CNT[12]
3 0 RW Y GRP0_OV_CNT[11]
2 0 RW Y GRP0_OV_CNT[10]
1 0 RW Y GRP0_OV_CNT[9]
0 0 RW Y GRP0_OV_CNT[8]
62 7 0 RW Y GRP1_OV_CNT[7] Group 1 count LSB
6 0 RW Y GRP1_OV_CNT[6]
5 0 RW Y GRP1_OV_CNT[5]
4 0 RW Y GRP1_OV_CNT[4]
3 0 RW Y GRP1_OV_CNT[3]
2 0 RW Y GRP1_OV_CNT[2]
1 0 RW Y GRP1_OV_CNT[1]
0 0 RW Y GRP1_OV_CNT[0]
63 7 0 RW Y CNT_DLTA_OV_1 Override enable for group 1 manual data rate selection
6 0 RW Y GRP1_OV_CNT[14] Group 1 count MSB
5 0 RW Y GRP1_OV_CNT[13]
4 0 RW Y GRP1_OV_CNT[12]
3 0 RW Y GRP1_OV_CNT[11]
2 0 RW Y GRP1_OV_CNT[10]
1 0 RW Y GRP1_OV_CNT[9]
0 0 RW Y GRP1_OV_CNT[8]
64 7 0 RW Y GRP0_OV_DLTA[3] Sets the PPM delta tolerance for the PPM counter lock check for group 0. Must also program channel Reg_0x67[7].
6 0 RW Y GRP0_OV_DLTA[2]
5 0 RW Y GRP0_OV_DLTA[1]
4 0 RW Y GRP0_OV_DLTA[0]
3 0 RW Y GRP1_OV_DLTA[3] Sets the PPM delta tolerance for the PPM counter lock check for group 1. Must also program channel Reg_0x67[6].
2 0 RW Y GRP1_OV_DLTA[2]
1 0 RW Y GRP1_OV_DLTA[1]
0 0 RW Y GRP1_OV_DLTA[0]
65 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
66 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
67 7 0 RW Y GRP0_OV_DLTA[4]
6 0 RW Y GRP1_OV_DLTA[4]
5 1 RW Y HV_LOCKMON_EN 1: Enable periodic monitoring of HEO/VEO for lock qualification.
0: Disable periodic HEO/VEO monitoring for lock qualification.
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
68 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
69 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 1 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
6A 7 0 RW Y VEO_LCK_THRSH[3] VEO threshold to meet before lock is established. The LSB step size is 4 counts of VEO.
6 0 RW Y VEO_LCK_THRSH[2]
5 1 RW Y VEO_LCK_THRSH[1]
4 0 RW Y VEO_LCK_THRSH[0]
3 0 RW Y HEO_LCK_THRSH[3] HEO threshold to meet before lock is established. The LSB step size is 4 counts of HEO.
2 0 RW Y HEO_LCK_THRSH[2]
1 0 RW Y HEO_LCK_THRSH[1]
0 1 RW Y HEO_LCK_THRSH[0]
6B 7 0 RW Y RESERVED RESERVED
6 1 RW Y FOM_A[6] Alternate Figure of Merit variable A. Max value for this register is 128.
5 0 RW Y FOM_A[5]
4 0 RW Y FOM_A[4]
3 0 RW Y FOM_A[3]
2 0 RW Y FOM_A[2]
1 0 RW Y FOM_A[1]
0 0 RW Y FOM_A[0]
6C 7 0 RW Y FOM_B[7] HEO adjustment for Alternate FoM, variable B
6 0 RW Y FOM_B[6]
5 0 RW Y FOM_B[5]
4 0 RW Y FOM_B[4]
3 0 RW Y FOM_B[3]
2 0 RW Y FOM_B[2]
1 0 RW Y FOM_B[1]
0 0 RW Y FOM_B[0]
6D 7 0 RW Y FOM_C[7] VEO adjustment for Alternate FoM, variable C
6 0 RW Y FOM_C[6]
5 0 RW Y FOM_C[5]
4 0 RW Y FOM_C[4]
3 0 RW Y FOM_C[3]
2 0 RW Y FOM_C[2]
1 0 RW Y FOM_C[1]
0 0 RW Y FOM_C[0]
6E 7 0 RW Y EN_NEW_FOM_CTLE 1: CTLE adaption state machine will use the alternate FoM
HEO_ALT = (HEO-B)*A*2VEO_ALT = (VEO-C)*(1-A)*2
The values of A,B,C are set in channel Reg_0x6B, 0x6C, and 0x6D.
The value of A is equal to the register value divided by 128.
The Alternate FoM = (HEOB)*A*2 + (VEO-C)*(1-A)*2
6 0 RW Y EN_NEW_FOM_DFE 1: DFE adaption state machine will use the alternate FoM.
HEO_ALT = (HEO-B)*A*2VEO_ALT = (VEO-C)*(1-A)*2
The values of A,B,C are set in channel Reg_0x6B, 0x6C, and 0x6D.
The value of A is equal to the register value divided by 128
The Alternate FoM = (HEOB)*A*2 + (VEO-C)*(1-A)*2
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
6F 7 0 RW Y MR_EN_LOW_DIVSEL_EQ Normally, during adaptation, if the divider setting is >2, then a fixed EQ setting, from Reg_0x3A will be used. However, if Reg_0x6F[7]=1, then an EQ adaptation will be performed instead.
6 0 RW Y RESERVED RESERVED
5 0 RW Y RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
70 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW Y EQ_LB_CNT[3] CTLE look-beyond count for adaptation
2 1 RW Y EQ_LB_CNT[2]
1 0 RW Y EQ_LB_CNT[1]
0 1 RW Y EQ_LB_CNT[0]
71 7 0 R N PRBS_INT When enabled by Reg_0x31[7], goes HI if a PRBS stream is detected. Clears on reading.
PRBS checker must be enabled with Reg_0x30[3].
Once cleared, if a PRBS error occurs, then the interrupt will again go HI. Clears on reading.
If signal detect is lost, this is considered a PRBS error, and the interrupt will go HI. Clears on reading.
6 0 R N RESERVED RESERVED
5 0 R N DFE_POL_1_OBS DFE tap 1 polarity observation
4 0 R N DFE_WT1_OBS[4] DFE tap 1 weight observation
3 0 R N DFE_WT1_OBS[3]
2 0 R N DFE_WT1_OBS[2]
1 0 R N DFE_WT1_OBS[1]
0 0 R N DFE_WT1_OBS[0]
72 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N DFE_POL_2_OBS Primary observation point for DFE tap 2 polarity
3 0 R N DFE_WT2_OBS[3] Primary observation point for DFE tap 2 weight
2 0 R N DFE_WT2_OBS[2]
1 0 R N DFE_WT2_OBS[1]
0 0 R N DFE_WT2_OBS[0]
73 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N DFE_POL_3_OBS Primary observation point for DFE tap 3 polarity
3 0 R N DFE_WT3_OBS[3] Primary observation point for DFE tap 3 weight
2 0 R N DFE_WT3_OBS[2]
1 0 R N DFE_WT3_OBS[1]
0 0 R N DFE_WT3_OBS[0]
74 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N DFE_POL_4_OBS Primary observation point for DFE tap 4 polarity
3 0 R N DFE_WT4_OBS[3] Primary observation point for DFE tap 4 weight
2 0 R N DFE_WT4_OBS[2]
1 0 R N DFE_WT4_OBS[1]
0 0 R N DFE_WT4_OBS[0]
75 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N DFE_POL_5_OBS Primary observation point for DFE tap 5 polarity
3 0 R N DFE_WT5_OBS[3] Primary observation point for DFE tap 5 weight
2 0 R N DFE_WT5_OBS[2]
1 0 R N DFE_WT5_OBS[1]
0 0 R N DFE_WT5_OBS[0]
76 7 0 RW Y POST_LOCK_VEO_THR[3] VEO threshold after LOCK is established
6 0 RW Y POST_LOCK_VEO_THR[2]
5 1 RW Y POST_LOCK_VEO_THR[1]
4 0 RW Y POST_LOCK_VEO_THR[0]
3 0 RW Y POST_LOCK_HEO_THR[3] HEO threshold after LOCK is established
2 0 RW Y POST_LOCK_HEO_THR[2]
1 0 RW Y POST_LOCK_HEO_THR[1]
0 1 RW Y POST_LOCK_HEO_THR[0]
77 7 0 RW N PRBS_GEN_POL_EN 1: Force polarity inversion on generated PRBS data
6 0 RW Y RESERVED RESERVED
5 0 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 1 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 0 RW N RESERVED RESERVED
78 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N SD_STATUS Primary observation point for signal detect status
4 0 R N CDR_LOCK_STATUS Primary observation point for CDR lock status
3 0 R N CDR_LOCK_INT Requires that channel Reg_0x79[1] be set.
1: Indicates CDR has achieved lock, lock goes from LOW to HIGH. This bit is cleared after reading. This bit will stay set until it has been cleared by reading.
2 0 R N SD_INT Requires that channel Reg_0x79[0] be set.
1: Indicates signal detect status has changed. This will trigger when signal detect goes from LOW to HIGH or HIGH to LOW. This bit is cleared after reading. This bit will stay set until it has been cleared by reading.
1 0 R N EOM_VRANGE_LIMIT_ERROR Goes high if GET_HEO_VEO indicates high during adaptation
0 0 R N HEO_VEO_INT Requires that channel Reg_0x36[6] be set.
1: Indicates that HEO/VEO dropped below the limits set in channel Reg_0x76 This bit is cleared after reading. This bit will stay set until it has been cleared by reading.
79 7 0 RW N RESERVED RESERVED
6 0 RW N PRBS_CHKR_EN 1: Enable the PRBS checker.
0: Disable the PRBS checker
5 0 RW N PRBS_GEN_EN 1: Enable the pattern generator
0: Disable the pattern generator
4 1 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW Y CDR_LOCK_INT_EN 1: Enable CDR lock interrupt, observable in channel Reg_0x78[3]
0: Disable CDR lock interrupt
0 0 RW Y SD_INT_EN 1: Enable signal detect interrupt, observable in channel Reg_0x78[3]
0: Disable signal detect interrupt
7A 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
7B 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
7C 7 0 R N PRBS_FIXED[7] Pattern generator user defined pattern LSB. MSB located at channel Reg_0x97.
6 0 R N PRBS_FIXED[6]
5 0 R N PRBS_FIXED[5]
4 0 R N PRBS_FIXED[4]
3 0 R N PRBS_FIXED[3]
2 0 R N PRBS_FIXED[2]
1 0 R N PRBS_FIXED[1]
0 0 R N PRBS_FIXED[0]
7D 7 0 RW Y CONT_ADAPT_HEO_CHNG_THRS[3] Limit for HEO change before triggering a DFE adaption while continuous DFE adaption is enabled.
6 1 RW Y CONT_ADAPT_HEO_CHNG_THRS[2]
5 0 RW Y CONT_ADAPT_HEO_CHNG_THRS[1]
4 0 RW Y CONT_ADAPT_HEO_CHNG_THRS[0]
3 1 RW Y CONT_ADAPT_VEO_CHNG_THRS[3] Limit for VEO change before triggering a DFE adaption while continuous DFE adaption is enabled.
(Refer to the Programming Guide for more details)
2 0 RW Y CONT_ADAPT_VEO_CHNG_THRS[2]
1 0 RW Y CONT_ADAPT_VEO_CHNG_THRS[1]
0 0 RW Y CONT_ADAPT_VEO_CHNG_THRS[0]
7E 7 0 RW Y CONT_ADPT_TAP_INCR[3] Limit for allowable tap increase from the previous base point
6 0 RW Y CONT_ADPT_TAP_INCR[2]
5 0 RW Y CONT_ADPT_TAP_INCR[1]
4 1 RW Y CONT_ADPT_TAP_INCR[0]
3 0 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 1 RW Y RESERVED RESERVED
7F 7 0 RW N EN_OBS_ALT_FOM 1: Allows for alternate FoM calculation to be shown in channel registers Reg_0x27, Reg_0x28 and Reg_0x29 instead of HEO and VEO
6 0 RW N RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 0 RW Y EN_DFE_CONT_ADAPT 1: Continuous DFE adaption is enabled
0: DFE adapts only during lock and then freezes
(Refer to the Programming Guide for more details)
3 1 RW Y CONT_ADPT_CMP_BOTH 1: If continuous DFE adaption is enabled, a DFE adaption will trigger if either HEO orVEO degrades
2 0 RW Y CONT_ADPT_COUNT[2] Limit for number of weights the DFE can look ahead in continuous adaption.
(Refer to the Programming Guide for more details)
1 1 RW Y CONT_ADPT_COUNT[1]
0 0 RW Y CONT_ADPT_COUNT[0]
80 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
81 7 1 R N RESERVED RESERVED
6 1 R N RESERVED RESERVED
5 1 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 1 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
82 7 0 RW N FREEZE_PRBS_CNTR 1: Freeze the PRBS error count to allow for readback.
0: Normal operation. Error counters is allowed to increment if the PRBS checker is properly configured
6 0 RW N RST_PRBS_CNTS 1: Reset the PRBS error counter.
0: Normal operation. Error counter is released from reset.
5 0 RW N PRBS_PATT_OV 1: Override PRBS pattern auto-detection. Forces the pattern checker to only lock onto the pattern defined in Reg_0x82[4:2].
0: Normal operation. Pattern checker will automatically detect the PRBS pattern
4 0 RW N PRBS_PATT[2] Used with the PRBS checker. Usage is enabled with Reg_0x82[5]. Select PRBS pattern to be checked:
000 - PRBS7
001 - PRBS9
010 - PRBS11
011 - PRBS15
100 - PRBS23
101 - PRBS31
110 - PRBS58
111 - PRBS63
3 0 RW N PRBS_PATT[1]
2 0 RW N PRBS_PATT[0]
1 0 RW N PRBS_POL_OV 1: Override PRBS pattern auto polarity detection. Forces the pattern checker to only lock onto the polarity defined in bit 0 of this register.
0: Normal operation, pattern checker will automatically detect the PRBS pattern polarity
0 0 RW N PRBS_POL Usage is enabled with Reg_0x82[1]=1
0: Forced polarity = true
1: Forced polarity = inverted
83 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N PRBS_ERR_CNT[10] PRBS checker error count
1 0 R N PRBS_ERR_CNT[9]
0 0 R N PRBS_ERR_CNT[8]
84 7 0 R N PRBS_ERR_CNT[7] PRBS checker error count
6 0 R N PRBS_ERR_CNT[6]
5 0 R N PRBS_ERR_CNT[5]
4 0 R N PRBS_ERR_CNT[4]
3 0 R N PRBS_ERR_CNT[3]
2 0 R N PRBS_ERR_CNT[2]
1 0 R N PRBS_ERR_CNT[1]
0 0 R N PRBS_ERR_CNT[0]
85 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
86 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
87 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
88 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
89 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
8A 7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
8B 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
8C 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
8D 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 1 RW N RESERVED RESERVED
1 1 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
8E 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW Y VGA_SEL_GAIN VGA selection bit :
1: VGA high-gain mode
0: VGA low-gain mode
(Refer to the Programming Guide for more details)
8F 7 0 R N EQ_BST_TO_EQ[7] Primary observation point for the EQ boost setting.
6 0 R N EQ_BST_TO_EQ[6]
5 0 R N EQ_BST_TO_EQ5]
4 0 R N EQ_BST_TO_EQ[4]
3 0 R N EQ_BST_TO_EQ[3]
2 0 R N EQ_BST_TO_EQ[2]
1 0 R N EQ_BST_TO_EQ[1]
0 0 R N EQ_BST_TO_EQ[0]
90 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
91 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
92 7:0 0 RW N RESERVED RESERVED
93 7:0 0 RW N RESERVED RESERVED
94 7:0 0 RW N RESERVED RESERVED
95 7 0 RW N SD_ENABLE 1: Force enable signal detect
0: Normal operation
6 0 RW N SD_DISABLE 1: Force disable signal detect
0: Normal operation
5 0 RW N DC_OFF_ENABLE 1: Force enable DC offset compensation
0: Normal operation
4 0 RW N DC_OFF_DISABLE 1: Force disable DC offset compensation
0: Normal operation
3 1 RW N EQ_ENABLE 1: Force enable the CTLE
0: Normal operation
2 0 RW N EQ_DISABLE 1: Force disable the CTLE
0: Normal operation
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
96 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 1 RW Y EQ_EN_LOCAL 1: Enable the ebuf for the local output. Can be set independently of other controls.
(Refer to the Programming Guide for more details)
2 0 RW Y EQ_EN_FANOUT 1: Enable the ebuf for the fanout. Can be set independently of other controls.
(Refer to the Programming Guide for more details)
1 0 RW Y EQ_SEL_XPNT 1: Indicates to a channel where it is getting its data from. 0 indicates local. 1-indicates from the cross.
(Refer to the Programming Guide for more details)
0 0 RW Y XPNT_SLAVE 1: Indicates to a channel if it needs to wait for the other channel to complete its lock/adaptation. The need for this condition comes up when input of one channel is routed to the other channel or multiple channels.
(Refer to the Programming Guide for more details)
97 7 0 R N PRBS_FIXED[15] Pattern generator user defined pattern MSB. LSB located at channel Reg_0x7C.
6 0 R N PRBS_FIXED[14]
5 0 R N PRBS_FIXED[13]
4 0 R N PRBS_FIXED[12]
3 0 R N PRBS_FIXED[11]
2 0 R N PRBS_FIXED[10]
1 0 R N PRBS_FIXED[9]
0 0 R N PRBS_FIXED[8]
98 7:6 0 RW N RESERVED RESERVED
5:0 0 RW Y RESERVED RESERVED
99 7 0 RW Y RESERVED RESERVED
6 0 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 1 RW Y RESERVED RESERVED
2 1 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 1 RW Y RESERVED RESERVED
9A 7 0 RW Y RESERVED RESERVED
6 0 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 1 RW Y RESERVED RESERVED
2 1 RW Y RESERVED RESERVED
1 1 RW Y RESERVED RESERVED
0 1 RW Y RESERVED RESERVED
9B 7 1 RW Y RESERVED RESERVED
6 1 RW Y RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 0 RW Y RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
9C 7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 1 RW Y RESERVED RESERVED
4 0 RW Y RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 1 RW Y RESERVED RESERVED
1 0 RW Y RESERVED RESERVED
0 0 RW Y RESERVED RESERVED
9D 7 1 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 1 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW Y RESERVED RESERVED
2 1 RW Y RESERVED RESERVED
1 0 RW Y RESERVED RESERVED
0 1 RW N RESERVED RESERVED
9E 7 0 RW Y CP_EN_IDAC_PD[2] Phase detector charge pump setting, when override is enabled. See reg_0C for other bits.
6 1 RW Y CP_EN_IDAC_PD[1]
5 0 RW Y CP_EN_IDAC_PD[0]
4 0 RW Y CP_EN_IDAC_FD[2] Frequency detector charge pump setting, when override is enabled. See reg_0C for other bits.
3 1 RW Y CP_EN_IDAC_FD[1]
2 0 RW Y CP_EN_IDAC_FD[0]
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
9F 7:0 0 R N NOT USED
A0 7:0 0 R N NOT USED
A1 7:0 0 R N NOT USED
A2 7:0 0 R N NOT USED
A3 7:0 0 R N NOT USED
A4 7:0 0 R N NOT USED
A5 7 0 RW Y PFD_SEL_DATA_PSTLCK[2] Output mode for when the CDR is in lock. For these values to take effect, Reg_0x09[5] must be set to 0, which is the default.
000: Raw Data
001: Retimed data (default)
100: PRBS Generator or Fixed Pattern Generator Data
101: 10M clock
111: Mute
All other values are reserved. (Refer to the Programming Guide for more details)
6 0 RW Y PFD_SEL_DATA_PSTLCK[1]
5 1 RW Y PFD_SEL_DATA_PSTLCK[0]
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
A6 7 0 RW N INCR_HIST_TMR Provides an option to increase EOM timer given by 0x2A[7:4] for histogram collection by +8 for selection values < 8
6 1 RW Y EOM_TMR_ABRT_ON_HIT Enables faster scan through the eye-matrix by moving on to the next matrix point as soon as hit is observed
Note: This bit does not affect when slope measurement are in progress
5 0 RW Y SLP_MIN_REQ_HITS[1] Minimum required hit count for registering a hit during slope measurements.
4 0 RW Y SLP_MIN_REQ_HITS[0]
3 0 RW Y LFT_SLP 0: allows slope measurement for the right side of the eye
1: allows slope measurement for the left side of the eye
2 0 RW Y TOP_SLP 0: allows slope measurement for the bottom side of the eye
1: allows slope measurement for the top side of the eye
1 1 RW Y DFE_BATHTUB_FOM Enables slope-based bathtub FoM for DFE adaptation
0 1 RW Y CTLE_BATHTUB_FOM Enables slope-based bathtub FoM for CTLE adaptation
A7 7:0 0 R N RESERVED RESERVED
A8 7:0 0 RW N RESERVED RESERVED
A9 7:0 0 RW Y RESERVED RESERVED